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STM32 F4xx Peripheral Models

Introduction

Microcontrollers (MCUs) for control applications typically contain peripheral modules such as Analog-to-Digital Converters (ADCs) and pulse width modulators (PWMs). These peripherals play an important role, since they act as the interface between the digital/analog signals of the control hardware and the control algorithms running on the processor. State-of-the-art MCUs often include peripherals with a multitude of advanced features and configurations to help implement complex sampling and modulation techniques.

When modeling power converters in a circuit simulator such as PLECS, it is desirable to represent the behavior of the MCU peripherals as accurately as possible. Basic Sample&Hold blocks and PWM modulators are useful for higher-level modeling. However, important details with regards to timing and quantization are lost when attempting to model an ADC with a basic zero-order hold (ZOH) block. For example, employing an idealized modulator to generate PWM signals can result in simulation results substantially different from the real hardware behavior.

Accurate peripheral models are even more important in the context of Processor-In-the-Loop (PIL) simulations. In this case, it is imperative to utilize peripheral models which are configurable exactly as the real implementations, i.e. by setting values in peripheral registers. By the same token, the inputs and outputs of the peripheral models must correspond precisely to the numerical representation in the embedded code.

The PLECS PIL library includes high-fidelity MCU peripheral models which work at the register level, and are therefore well-suited for PIL simulations. Furthermore, certain blocks have a second implementation with a graphical user interface (GUI) that automatically determines the register configurations based on text-based parameter selections.

Subsequent sections describe the PLECS peripheral components in detail and highlight modeling assumptions and limitations. When documenting peripheral register settings, the following color coding is used:

  1. Grey (dark shading): No effect on the model behavior
  2. Green (light shading): Register cell affects the behavior of the model

System Timer for PWM Generation (Output Mode)

The PLECS peripheral library provides two blocks for the STM32 F4 system timer used in output mode. One block has a register-based configuration mask and a second block features a GUI. In both cases, you should distinguish between registers configured in the parameter mask and inputs to the block. Mask parameters are fixed (static) during a simulation and correspond to the configurations which the embedded software uses during the initialization phase. Inputs are dynamically changeable while the simulation is running. The fixed configuration can be entered either using a register-based approach or a GUI, while the dynamic values supplied at the inputs must correspond to raw register values. The figure below shows the block and its parameters for the register-based version.

pict   [Picture]
Register-based Timer model for output mode

As depicted above, the block can be configured directly using the registers of the hardware module, making it possible to exactly mirror the configuration applied to the target. Also as shown, either hexadecimal, decimal or binary representation can be used to enter the configuration.

Timer Subtypes

The STM32 F4 MCU's provide several subtypes of timers which can be used for input capture, output compare and PWM generation functionalities. In the presented model, all subtypes listed below are combined in one module and can be chosen via the component mask:

The focus of this model is the timer output behavior meaning that all input functionalities are disregarded. This corresponds to the hardware behavior with all TIM_CCMRx.CCyS cells being set to 00. Further, the One-Shot mode of the module is not supported. In the following sections, the common part of all subtypes is explained together with the models limitations. Further, the differences between the subtypes are described in more detail.

General Counter Behavior

The base of all timer modules is an auto-reload counter driven by a prescaled counter clock CK_CNT. The period of this time base clock is determined by the counter clock frequency CK_PSC and the prescaler register TIM_PSC, both configurable in the mask, as follows:

TCKxCNT  = TIM-xPSC-+-1-
             CK xPSC

The counter either operates in Edge-aligned mode with configurable direction or in Center-aligned mode. In addition to the general counter functionality, the module also generates output compare interrupt flags when the counter matches the values stored in the CCRx registers. Those flags are later used to determine the output levels of the timer module.

Edge-aligned mode

In upcounting direction, the counter counts from 0 to the counter period value TIM_ARR and generates an update event UEV simultaneous to the counter overflow.

[Picture]
Edge-aligned mode / Upcounting [1]

In downcounting direction, the counter counts from TIM_ARR to 0 and generates an update event (UEV ) simultaneous to the counter underflow.

[Picture]
Edge-aligned mode / Downcounting [1]

In Edge-aligned mode, the counter period and therefore the PWM period is calculated as:

TPWM  = TCKxCNT ⋅(TIM xARR  + 1)

Center-aligned mode

In this mode, the counter alternates its direction and generates an update event (UEV ) at the counter under- and overflow. In the model, the counter always starts in upcounting direction.

[Picture]
Center-aligned mode [1]

For Center-aligned mode, the PWM period is calculated as:

TPWM  = TCKxCNT  ⋅2⋅TIM xARR

For all modes, the timer model operates in preloaded mode, meaning that the used configuration is updated simultaneously to the update events. The Repetition Counter functionality is not supported in the model.

[Picture]
Events used for configuration update [1]

In other words, all input terminals of the model, except the CCER register, are sampled with the instants of the update events.

The timer mode, direction and output compare flag behavior can be set jointly using the TIM_CR1 register.

pict
Timer Mode Configuration

The CKD field only has an effect on the subtypes with PWM dead time generation and is therefore described in a later section. The register cell CMS can be used to determine the counter mode and the output compare flag behavior.

In Edge-aligned mode, the DIR bit determines the counter direction.

The module assumes the timer as always active and to be operated in preloaded mode with the update event generation always enabled. Therefore, the following settings are mandatory when using the register-based version.

Interrupt Flags

The timer module can generate interrupt flags at the CCxIF and UIF output terminals. Those flags are based on the counter compare and update event flags and can be used in the model to, i.e., trigger an ADC conversion or a new control step via the PIL block. Note that in the model those flags are implemented as pulses.

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Interrupt enable register

The interrupt flags can be enabled with the bits of the TIM_DIER register.


Note  Only the four channel subtype implementations make use of all CCxIE fields.

Output Mode Controller

The output-mode controller generates up to 4 reference signals OCyREF based on the output compare flags of the counter.

[Picture]
Output Mode Controller for OCyREF [1]

The controller implements several output modes defining the behavior of OCyREF. With the register fields TIM_CCMRx.OCyM, the mode of each reference signal can be specified separately.

Because the reference signal mode is supposed to be changed during simulation, the OCyM fields can be accessed via the input terminals. Note that those are also updated with the update events generated by the timer.

The hardware options to externally clear the reference signal are not supported in the model. Further, the break function of the timer is not part of the model assuming the flag BDTR.MOE is always set. Therefore it is mandatory to set MOE to 1   while using the resister-based version.

The options available in the output stage majorly depend on the timer subtype and therefore are discussed in the subsequent sections. The configuration of all output stages is done with the CCER register.


Note  The CCER is accessed via the input terminals and is not preloaded. This means that a change on the CCER input directly effects the outputs.

4 channel Advanced Timer

The Advanced Timer consists of a timer and a 4 channel output stage. The timer has a width of 16-bit and can be operated in Edge-aligned (up and down) as well as Center-aligned mode. For channels 1 to 3, the output stage enables complementary outputs with dead time and configurable polarity.

[Picture]
Output stage of Advanced Timer (channel 1 to 3) [1]

For channel 4, the output stage shown below only supports configurable polarity.

[Picture]
Output stage of Advanced Timer (channel 4) [1]

The CCER register can be used to configure all channels of the output stage separately.

pict
Channel-wise configuration of output stage

With the CCxP and CCxNP fields, the polarity of the output signal can be inverted.

With the CCxE and CCxNE bits, the output can be enabled.

Those bits further effect the output stage behavior for channels 1 to 3. The table below shows this for both outputs operated with equal polarity.

CCxNECCxEBehavior
00OCx & OCxN inactive
01OCx = OCxRef, OCxN inactive
10OCx inactive, OCxN = OCxRef
11Complementary output mode with Dead time

The dead time for each positive flank in OCx and OCNx is configured with the TIM_BDTR register.

pict
Dead time configuration

The dead time (DT) can be calculated based on the cell DTG as shown below. The bits DTG[7:5] determine the formula used for its calculation.

The dead time clock tDTS   is related to the timer clock period TCKxCNT   and can be configured with the field CKD of the TIM_CR1 register.

This subtype implementation uses the full set of inputs, outputs and configuration registers.

4 channel General Purpose Timer

This subtype is available with a 16-bit or 32-bit counter implementation both supporting Edge-aligned (up and down), as well as Center-aligned modes. The 4 channel output stage shown below only supports configurable polarity.

[Picture]
Output stage of general purpose timer (channel 1/4) [1]

The CCER register can be used to configure all channels of the output stage separately.

pict
Channel-wise configuration of output stage

With the CCxP bits, the polarity of the output signal can be inverted.

With the CCxE and CCxNE bits, the output can be enabled.


Note The CCxNP bits have no effect on the model.

The terminals used by this subtype are shown in the table below.

TerminalUtilizedUnused
InputCCR1 - CCR4, ARR, CCER, OC1M - OC4Mx
OutputOC1 - OC4, CC1IF- CC4IF, UEV OC1N - OC3N

Unused mask registers, register cells and further limitations are listed below.

2 channel General Purpose Timer

This subtype contains a 16-bit counter only supporting Edge-aligned, Upcounting mode. The 2 channel output stage shown below only supports configurable polarity.

[Picture]
Output stage of general purpose timer (channel 1/2) [1]

The CCER register can be used to configure both channels of the output stage separately.

pict
Channel-wise configuration of output stage

With the CCxP bits, the polarity of the output signal can be inverted.

With the CCxE and CCxNE bits, the output can be enabled.


Note The CCxNP bits have no effect on the model.

The terminals used by this subtype are shown in the table below.

TerminalUtilizedUnused
InputCCR1 - CCR2, ARR, CCER, OC1M - OC2M CCR3 - CCR4, OC3M-OC4M
OutputOC1 - OC2, CC1IF - CC2IF, UEV OC3 - OC4, OC1N - OC3N, CC3IF - CC4IF

Unused mask registers, register cells and further limitations are listed below.

1 channel General Purpose Timer

This subtype contains a 16-bit counter only supporting Edge-aligned, Upcounting mode. The single channel output stage shown below only supports configurable polarity.

[Picture]
Output stage of general purpose timer (channel 1/1) [1]

The CCER register can be used to configure single channel output stage.

pict
Configuration of the output stage

With the CCxP bits, the polarity of the output signal can be inverted.

With the CCxE and CCxNE bits, the output can be enabled.


Note The CC1NP bit has no effect on the model.

The terminals used by this subtype are shown in the table below.

TerminalUtilizedUnused
InputCCR1 - CCR2, ARR, CCER, OC1M - OC2M CCR3 - CCR4, OC3M-OC4M
OutputOC1 - OC2, CC1IF - CC2IF, UEV OC3 - OC4, OC1N - OC3N, CC3IF - CC4IF

Unused mask registers, register cells and further limitations are listed below.

GPIO Mode

In case that an output enable circuit is configured as inactive, the output level is determined by the GPIO Mode. To mimic this in the simulation model, the parameter GPIO Mode is available in the register-based version.

pict
Configuration of GPIO Mode

With the bits OCx and OCxN, the corresponding output mode can be set.


Note  This Register is available only in the simulation.

Analog-Digital Converter (ADC)

The PLECS peripheral library provides two blocks for the STM32 F4 single ADC module, one with a register-based configuration mask and a second with a GUI. The figure below shows the appearance of the block.

pict
ADC module model

The register-based version allows the user to directly enter register values in decimal, binary, or hexadecimal notation. For convenience, the peripheral library also provides a component with a GUI to simplify the configuration.

Both ADC blocks interface with other PLECS components over the following terminal groups.

ADC Module Overview

The PLECS single ADC model contains the most relevant features of the MCU peripheral.

[Picture]
Overview of the STM F4 ADC module [1]

The ADC model implements these logical submodules:

For simplicity, the external trigger configuration shown in the figure above is neglected. The trigger to the regular and injected channels are directly accessed via the corresponding input terminals. Further, the Analog Watchdog functionalities as well as the Watchdog and DMA overrun interrupts are not part of the model. Due to simulation efficiency reasons, the ADC can not be operated in continuous conversion mode.

ADC Converter with Result Registers

The ADC module contains a converter with configurable resolution. An external voltage reference is used which can be defined in the component mask.

The period of an ADC clock, and therefore the time base for the module, is determined based on PCLK2 and the clock divider specified in the ADC_CCR register.

pict
ADC_CCER Register structure

By using the ADCPRE bits the ADC time base can be specified as follows:

ADCPRE[1]ADCPRE[0] ADC clock
00PCLK2 / 2
01PCLK2 / 4
10PCLK2 / 8
11PCLK2 / 16

The resolution of the converter can be specified with the fields RES of the ADC_CR1 register given in the next section. This also influences the amount of ADC clock cycles needed for a conversion. With the RES bits the resolution can be specified as shown in the table below.

RES[1]RES[0] ResolutionConversion length
0012 bit15 ADCCLK cycles
0110 bit13 ADCCLK cycles
108 bit11 ADCCLK cycles
116 bit9 ADCCLK cycles

For the regular channels, the hardware ADC contains a single 16-bit result register ADC_DR. The results of multiple, sequential regular group conversions are typically moved to the SRAM on the fly via the DMA controller. To simplify this, the ADC_DR terminal provides the conversion result for each of the 16 regular group members separately. For the injected channels, the ADC_JDR terminal provides access to the contents of all four ADC_JDRx registers.

The component only supports the right aligned result representation mode meaning that ADC_CR2.ALIGN always needs to be set to 0. In addition to this, the model provides an option to represent the conversion results as quantized double integers, which can be chosen with the mask parameter Output Mode.

ADC Sample Logic

The ADC model supports the single, scan and discontinuous conversion modes as well as auto-injected conversions. The continuous conversion mode is not supported due to simulation efficiency reasons. The ADC_CR1 and ADC_CR2 registers can be used to choose and control the used conversion mode.

pict
ADC_CR1 Register structure

The DISCNUM field defines the number of regular channels converted after a trigger to the regular group was received in discontinuous mode.

CHSELInput
0001 channel
0012 channels
......
1107 channels
1118 channels

The bit JDISCEN determines the discontinuous mode for injected channels:

With DISCEN, the discontinuous mode can be enabled for regular channels:

The bit JAUTO can be used to automatically trigger an injected group conversion after the regular group was finished:


Note  Be aware that JDISCEN and DISCEN exclude each other and JAUTO can not be used with discontinuous mode or triggers to the injected group.

With the bit SCAN, the user can activate the scan mode of the component allowing multiple conversion triggered by a single event.

If none of the bits JDISCEN,DISCEN and SCAN is set, the adc module operates in single conversion mode. The bits JEOCIE and EOCIE are further described in the interrupt section.

For more information about the different conversion modes please refer to [2].

pict
ADC_CR2 Register structure

The field EOCS configures when the EOC flag is set while not in single conversion mode.


Note  The adc model assumes the adc not to operate in continuous conversion mode and to be always active. Therefore ADC_CR2.CONT needs to be cleared and ADC_CR2.ADON needs to be set while using the register-based configuration.

For every analog input, the sample time of a conversion can be configured separately using the ADC SMPRx registers.

pict
ADC_SMPRx Register structure

Note that SMP16-SMP18 have no effect because the measurements for the temperature sensor as well as the internal reference and the battery voltage are not part of the model. For every other channel, the sampling time can be configured as follows:

SMPxSampling Time
0003 cycles
00115 cycles
01028 cycles
01156 cycles
10084 cycles
101112 cycles
110144 cycles
111480 cycles

The ADC operates as a sequencer which has a maximum sequence of 16 conversion for the regular group and 4 conversions for the injected group. The input sampled by each group element as well as the sequence length can be configured via the ADC_SQRx and the ADC_JSQR registers.

pict
ADC_SQRx Register structure

The length of the regular sequence is defined by the field L.

LSequence lengthConverted elements / ADC_DR
00001 conversion[SQ1]
00012 conversion[SQ1 SQ2]
.........
111116 conversions[SQ1 SQ2 ... SQ16]

pict
ADC_JSQR Register structure

The length of the injected sequence is defined by the field JL.

JLSequence length Converted Elements / ADC_JDR
001 conversion[JSQ4]
012 conversion[JSQ3 JSQ4]
.........
114 conversions[JSQ1 JSQ2 JSQ3 JSQ4]

After the last conversion is finished, the sequencer wraps around and restarts with the first element after the next trigger was received.

For every sequence element, the sampled input can be specified via the corresponding SQx or JSQx fields as follows:

SQx/JSQxInput
x0000ADC_IN0
x0001ADC_IN1
......
x1111ADC_IN15


Note  The terminals ADC_DR and ADC_JDR are auto-size output terminals. This means that the width of the terminals is defined by J or JL as shown in the upper tables.

ADC Interrupt Logic

The ADC module also has a connection to the NVIC of the STM F4 MCU. The EOC flag is set when either the regular channel or the injected channel indicates an end of conversion. The JEOC flag is set when the injected group indicates a finished conversion. The fields ADC_CR1.EOCIE and ADC_CR1.JEOCIE can be used to configure the adc to provide an interrupt pulse to the corresponding output terminals.

Even if there typically won't be a model of the NVIC within the simulation, those pulses can i.e. be used to trigger the PIL block modeling a control step triggered by a finished adc conversion.

Reference

1 - Literature Source: STM32 Reference Manual [RM0090]