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TI C2000 Peripheral Models

Introduction

Microcontrollers (MCUs) for control applications typically contain peripheral modules such as Analog-to-Digital Converters (ADCs) and pulse width modulators (PWMs). These peripherals play an important role, since they act as the interface between the digital/analog signals of the control hardware and the control algorithms running on the processor. State-of-the-art MCUs often include peripherals with a multitude of advanced features and configurations to help implement complex sampling and modulation techniques.

When modeling power converters in a circuit simulator such as PLECS, it is desirable to represent the behavior of the MCU peripherals as accurately as possible. Basic Sample&Hold blocks and PWM modulators are useful for higher-level modeling. However, important details with regards to timing and quantization are lost when attempting to model an ADC with a basic zero-order hold (ZOH) block. For example, employing an idealized modulator to generate PWM signals can result in simulation results substantially different from the real hardware behavior.

Accurate peripheral models are even more important in the context of Processor-In-the-Loop (PIL) simulations. In this case, it is imperative to utilize peripheral models which are configurable exactly as the real implementations, i.e. by setting values in peripheral registers. By the same token, the inputs and outputs of the peripheral models must correspond precisely to the numerical representation in the embedded code.

The PLECS PIL library includes high-fidelity MCU peripheral models which work at the register level, and are therefore well-suited for PIL simulations. Furthermore, certain blocks have a second implementation with a graphical user interface (GUI) that automatically determines the register configurations based on text-based parameter selections.

Subsequent sections describe the PLECS peripheral components in detail and highlight modeling assumptions and limitations. When documenting peripheral register settings, the following color coding is used:

  1. Grey (dark shading): No effect on the model behavior
  2. Green (light shading): Register cell affects the behavior of the model

Enhanced Pulse Width Modulator (ePWM) Type 1

The PLECS peripheral library provides two blocks for the TI ePWM type 0/1 module. One block has a register-based configuration mask and a second block features a graphical user interface. In both cases, you should distinguish between registers configured in the parameter mask and inputs to the block. Mask parameters are fixed (static) during simulation and correspond to the configurations which the embedded software makes during the initialization phase. Inputs are dynamically changeable while the simulation is running. The fixed configuration can be entered either using a register-based approach or a graphical user interface, while the dynamic values supplied at the inputs must correspond to raw register values. The figure below shows the block and its parameters for the register-based version.

pict   [Picture]
Register based ePWM module model

As depicted above, the block can be configured directly using the registers of the hardware module, making it possible to exactly mirror the configuration applied to the target. Also as shown, either hexadecimal, decimal or binary representation can be used to enter the configuration.

Supported Submodules and Functionalities

The ePWM type 0/1 module consists of several submodules:

[Picture]
Submodules of the ePWM type 1 module [1]

The PLECS ePWM model accurately reflects the most relevant features of the following submodules:

Time-Base (TB) Submodule

This submodule realizes a counter that can operate in three different modes for the generation of asymmetrical and symmetrical PWM signals. The three modes, up-count, down-count, and up-down-count, are visualized below.

[Picture]
Counter modes and resulting PWM frequencies [1]

In up-count mode, the counter is incremented from 0   to a counter period TBPRD using a counter clock with period TTBCLK  . When the counter reaches the period, the subsequent count value is reset to zero and the sequence is repeated. When the counter is equal to zero or the period value, the submodule produces a pulse of one counter clock period, which, together with the actual counter direction, is sent to the subsequent Action Qualifier submodule.

The period of the timer clock can be calculated based on the system clock (SYSCLKOUT) and the two clock dividers (CLKDIV and HSPCLKDIV ) by:

T       = CLKDIV--⋅HSPCLKDIV----
 TBCLK        SYSCLKOUT

The resulting PWM period further depends on the counting mode, the counter period (TBPRD) and the counter clock period as depicted in the figure above.

While the system clock and the period counter value are separately defined in the mask parameters, the counter mode and the clock divider are jointly configured in the TBCTL register.

pict
TBCTL Register Configuration

The CLKDIV and HSPCLKDIV cells select the desired clock dividers and the CTRMODE cell defines the counter mode. Only counter modes 00, 01, and 10 are supported by the PLECS ePWM model.

Example Configuration - Step 1

This example is based on the parameter mask shown at the beginning of this chapter and will be further developed in subsequent sections. The TBCTL register is configured to:

TBCTL  = 1024  ^=  0 0 0 0 0 1    0 0    0 0 0 0 0 0 0 0
                       C◟L◝K◜DI◞V HSP◟C◝L◜◞KDIV          CT◟R◝M◜O◞DE

According to this configuration, the time base submodule is operating in the up-count mode with a timer clock period twice the system-clock period. The resulting PWM signal has the following period:

T     = (TBPRD  + 1) ⋅ CLKDIV-⋅HSPCLKDIV----= 187.525 μs.
  PWM                     SYSCLKOUT

Counter-Compare (CC) Submodule

This submodule is responsible for generating the pulses CTR = CMPA and CTR = CMPB used by the Action-Qualifier submodule. In a typical application, the compare values change continuously during operation and therefore need to be part of the dynamic configuration (block inputs). The PLECS implementation only supports the shadow mode for the CMPx registers, i.e. the content of a CMPx register is only transferred to the internal configuration at reload events. The reload events are specified in the CMPCTL register.

pict
CMPCTL Register Configuration

For efficiency, the PLECS ePWM model only supports the following combinations of counter mode and reload events:

CTRMODELOADAMODELOADBMODE
Up-countCTR = 0CTR = 0
Down-countCTR = PRDCTR = PRD
Up-down-count CTR = 0
or
CTR = 0 or CTR = PRD
CTR = 0
or
CTR = 0 or CTR = PRD

Furthermore, only coinciding configurations for LOADAMODE and LOADBMODE are supported.

In the example configuration, the CMPCTL register needs to be set to 0   because the counter is operating in up-count mode.

Action-Qualifier (AQ) Submodule

This submodule sets the EPWMx outputs based on the flags generated by the Time-Base and Counter-Compare submodules. The AQCTLx registers configure the actions to be performed at the different events. Similiar to the CMPx registers, the AQCTLx registers are operated in shadow mode and are reloaded at both the zero and the period event.

[Picture]
ePWM timing example [1]

The figure above shows an example (Case 2) where the ePWM output is set to high at the CTR = CMPA event. As depicted, an output change always lags the event by one counter clock period. The following shows the structure of the AQCTL register.

pict
AQCTL Register Configuration

Actions depend on the counter direction. For example, the register cell CBD defines what happens to the corresponding ePWMx output when the counter equals CMPB, when the counter is counting down. The following configurations exist:

If events occur simultaneously, the ePWM module respects a priority assignment based on the counter mode. The following figures show the Action-Qualifier prioritization.

[Picture]
Action-Qualifier prioritization in up-down-count mode [1]

[Picture]
Action-Qualifier prioritization in up-count mode [1]

[Picture]
Action-Qualifier prioritization in down-count mode [1]

Notice how software-forced events have the highest priority in all three count modes. Software forcing is configured by the Action-Qualifier-Continous-Software-Force-Register (AQCSFRC), provided as an input to the PLECS block to allow dynamic register configuration.

pict
AQCSFRC Register Configuration

The figure above shows the relevant cells of the register where CSFA and CSFB can be used to force an output. The following configurations are supported:

As illustrated in the previous ePWM timing example, the change of an ePWMx output lags the change of AQCSFRC by one counter clock period. Similar to the previously described registers with dynamic configuration, the AQCSFRC register is operated in shadow mode. The reload events can be defined with the AQSFRC register.

pict
AQSFRC Register Configuration

The supported modes for RLDCSF are listed below.

Immediate mode for loading is not supported due to implementation efficiency reasons.

Example Configuration - Step 2

The following figure shows an example using the actions defined by the AQCTL registers. Refer to [1] for a detailed explanation of the action symbols.

[Picture]
Desired ePWMA and ePWMB output signals [1]

To realize the above ePWM signals, the dynamic configuration must be set as follows:

CMPA  = 3500,CMPB  = 2000,AQCSFRC   = 0

Furthermore, the Action-Qualifier must be set as shown below:

AQCTLA   = 18   ^=  0 0 0 0 ◟0◝ 0◜◞0◟◝0◜◞ 0◟◝0◜◞ 0◟◝◜1◞ 0◟◝◜0◞◟1◝ 0◜◞
                          CBD CBU  CAD CAU  PRDZRO

AQCTLB   = 258  ^=  0 0 0 0 ◟0◝ 0◜◞0◟◝1◜◞ 0◟◝0◜◞ 0◟◝◜0◞ 0◟◝◜0◞◟1◝ 0◜◞
                          CBD CBU  CAD CAU  PRDZRO

Event-Trigger (ET) Submodule

This submodule utilizes the signals generated by the Time Base and Counter Compare submodules to generate events (pulses) at the ePWMSOCx outputs. Such pulses can trigger an ADC conversion or invoke the execution of a control algorithm or PIL block. For each ePWMSOC channel, the Event Trigger module provides an internal 2-bit counter which permits a downsampling of events. The following diagram shows the internal structure for the example of SOCA.

[Picture]
Event Trigger Logic [1]

As can be seen, the counter is being incremented using one of the source signals on the right-hand side. The incrementing source signal is selected by the SOCxSEL field. An SOC pulse is generated when the SOCxCNT reaches its configurable period (SOCxPRD) and pulse generation is activated by the SOCx flag. The configuration for both the SOCA and SOCB portion of the Event Trigger is set by the registers ETSEL and ETPS, which are realized as static parameters of the PLECS model.

The ETSEL register has the following structure.

pict
ETSEL Register Configuration

The SOCxEN bits activate or deactivate the SOCx pulses. The SOCxSEL cells determine the source for the event trigger counter. Note, SOCxSEL   = 000   is not supported in the model.

This figure shows the structure of the ETPS register.

pict
ETPS Register Configuration

The SOCxCNT cells allow initialization of the event counter. The SOCxPRD bits determine the number of events that must occur before an SOCx pulse is generated. Refer to [1] for detailed information regarding the configuration of the ETPS register.

Example Configuration - Step 3

A possible use case for the Event-Trigger submodule is to generate a SOCA pulse every second time the TB-counter meets the CMPA value. To achieve this behavior, the ET is configured as follows.

ETSEL  = 0xC00    ^=  0 0 0 0  1     1-0 0    0 0 0 0 0 0 0 0
                           SO◟C◝A◜E◞N SO◟C◝A◜S◞EL

This setting enables the SOCA pulses and uses the CTR = CMPA event for incrementing the ET-counter. Note that SOCB pulses are completely disabled in this example.

ETPS   = 512   ^=  0 0 0 0   0 0     1 0    0 0 0 0 0 0 0 0
                         SO◟C◝A◜C◞NT SO◟C◝A◜P◞RD

Dead-Band Submodule

The role of this submodule is to add programmable delays to rising and falling edges of the ePWM signals and to generate signal pairs with configurable polarity. The figure below depicts the internal structure of the Dead-Band submodule.

[Picture]
Dead-Band Logic [1]

As shown, the PWMx signals from the Action-Qualifier submodule are post-processed based on the DBCTL register settings. Furthermore, the delay times are programmables by the registers DBRED and DBFED for the rising and falling edge delay, respectively. The structure of the DBCTL register is shown in the following block diagram.

pict
DBCTL Register Configuration

The submodule register cells allow for the following settings:

Refer to [1] for detailed information regarding the configuration of the DBCTL register.

Example Configuration - Step 4

In the sample configuration, the signal EPWMB is selected as the source for both delay counters. Further, both the rising and falling edge of the outputs are delayed by 10 counter clock periods and the polarities are not inverted. The DBCTL register therefore should be configured as follows.

DBCTL  = 0b110011 ^=  0 0 0 0 0 0 0 0 0 0 1◟◝1◜◞ 0◟◝0◜◞      1◟◝ 1◜◞
                                    INxMODE  POLxSELOUTxMODE

With the HALFCYCLE bit set to zero, the DBRED and DBFED must be configured to:

DBRED  = 10 , DBFED   = 10

Enhanced Pulse Width Modulator (ePWM) Type 4

The PLECS peripheral library provides two blocks for the TI ePWM type 4 module. One block has a register-based configuration mask and a second block features a graphical user interface. In both cases, you should distinguish between registers configured in the parameter mask and inputs to the block. Mask parameters are fixed (static) during simulation and correspond to the configurations which are initialized by the embedded software at startup. Inputs are dynamically changeable while the simulation is running. The fixed configuration can be entered either using a register-based approach or a graphical user interface, while the dynamic values supplied at the inputs must correspond to raw register values. The figure below shows the block and its parameters for the register-based version.

pict
Register based ePWM module model

As depicted above, the block can be configured directly using the registers of the hardware module, making it possible to exactly mirror the configuration applied to the target. Also as shown, either hexadecimal, decimal or binary representation can be used to enter the configuration.

Supported Submodules and Functionalities

The ePWM type 4 module consists of several submodules:

[Picture]
Submodules of the ePWM type 4 module [4]

The PLECS ePWM model accurately reflects the most relevant features of the following submodules:

Time-Base (TB) Submodule

This submodule realizes a counter that can operate in three different modes for the generation of asymmetrical and symmetrical PWM signals. The three modes, up-count, down-count, and up-down-count, are visualized below.

[Picture]
Counter modes and resulting PWM frequencies [4]

In up-count mode, the counter is incremented from 0   to a counter period TBPRD using a counter clock with period TTBCLK  . When the counter reaches the period, the subsequent count value is reset to zero and the sequence is repeated. When the counter is equal to zero or the period value, the submodule produces a pulse of one counter clock period, which, together with the actual counter direction, is sent to the subsequent Action Qualifier submodule.

In the type 4 ePWM module, the system clock (SYSCLKOUT) can be divided further to generate the EPWM clock (EPWMCLK). This is determined by the EPWMCLKDIV bit in the PERCLKDIVSEL register and the system clock by the following formula:

EPWMCLK    = ---SYSCLKOUT------
             1 + EPWMCLKDIV

The period of the timer-base module clock (TBCLK) can be calculated based on the EPWM clock (EPWMCLK) and the two clock dividers (CLKDIV and HSPCLKDIV ) by:

          CLKDIV  ⋅HSPCLKDIV
TTBCLK  = -----EPWMCLK----------

The resulting PWM period further depends on the counting mode, the counter period (TBPRD) and the counter clock period as depicted in the figure above.

While the system clock and the period counter value are separately defined in the mask parameters, the counter mode and the clock divider are jointly configured in the TBCTL register.

pict
TBCTL Register Configuration

The CLKDIV and HSPCLKDIV cells select the desired clock dividers and the CTRMODE cell defines the counter mode.

Only counter modes 00, 01, and 10 are supported by the PLECS ePWM type 4 model.

Example Configuration - Step 1

This example is based on the parameter mask shown at the beginning of this chapter and will be further developed in subsequent sections.

The EPWM-clock period is set equal to the system-clock period by configuring the EPWMCLKDIV bit to zero.

The TBCTL register is configured to:

TBCTL  = 1024  ^=  0 0 0 0 0 1    0 0    0 0 0 0 0 0 0 0
                       C◟L◝K◜DI◞V HSP◟C◝L◜◞KDIV          CT◟R◝M◜O◞DE

According to this configuration, the time-base submodule is operating in the up-count mode with a timer clock period twice the EPWM-clock period. The resulting PWM signal has the following period:

T     = (TBPRD  + 1) ⋅ CLKDIV-⋅HSPCLKDIV----= 187.525 μs.
  PWM                      EPWMCLK

Counter-Compare (CC) Submodule

This submodule is responsible for generating the pulses CTR = CMPA, CTR = CMPB, CTR = CMPC and CTR = CMPD used by the Action-Qualifier submodule. In a typical application, the compare values change continuously during operation and therefore need to be part of the dynamic configuration (block inputs). The PLECS implementation only supports the shadow mode for the CMPx registers, i.e. the content of a CMPx register is only transferred to the internal configuration at reload events.

The reload events are specified in the CMPCTL and CMPCTL2 registers.

pict
CMPCTL Register Configuration

pict
CMPCTL Register Configuration

For efficiency, the PLECS ePWM model only supports the following combinations of counter mode and reload events:

CTRMODELOADAMODELOADBMODELOADCMODELOADDMODE
Up-countCTR = 0CTR = 0CTR = 0CTR = 0
Down-countCTR = PRDCTR = PRDCTR = PRDCTR = PRD
Up-down-count CTR = 0
or
CTR = 0 or CTR = PRD
CTR = 0
or
CTR = 0 or CTR = PRD
CTR = 0
or
CTR = 0 or CTR = PRD
CTR = 0
or
CTR = 0 or CTR = PRD

Furthermore, only coinciding configurations for LOADAMODE, LOADBMODE, LOADCMODE and LOADDMODE are supported.

In the example configuration, the CMPCTL and CMPCTL2 registers need to be set to 0   because the counter is operating in up-count mode.

Action-Qualifier (AQ) Submodule

This submodule sets the EPWMx outputs based on the flags generated by the Time-Base and Counter-Compare submodules. The AQCTLx and AQCTLx2 registers configure the actions to be performed at the different events. Similiar to the CMPx registers, the AQCTLx and AQCTLx2 registers are operated in shadow mode and are reloaded at both the zero and the period events.

[Picture]
ePWM timing example [4]

The figure above shows an example (Case 2) where the ePWM output is set to high at the CTR = CMPA event. As depicted, an output change always lags the event by one counter clock period. The following shows the structure of the AQCTLx register.

pict
AQCTLx Register Configuration

An output change can also be made using the T1 and T2 events. The AQCTLx2 register can be configured to change output when a T1 or T2 event occurs and depending on the direction of the counter at that instant. It is assumed that an output change always lags the event by one counter clock period. The following figure shows the structure of the AQCTLx2 register.

pict
AQCTLx2 Register Configuration

Actions depend on the counter direction. For example, the register cell CBD defines what happens to the corresponding ePWMx output when the counter equals CMPB, and when the counter is counting down. The following configurations exist:

If events occur simultaneously, the ePWM module respects a priority assignment based on the counter mode. The following figures show the Action-Qualifier prioritization.

[Picture]
Action-Qualifier prioritization in up-down-count mode [4]

[Picture]
Action-Qualifier prioritization in up-count mode [4]

[Picture]
Action-Qualifier prioritization in down-count mode [4]

Notice how software-forced events have the highest priority in all three count modes. Software forcing is configured by the Action-Qualifier-Continous-Software-Force-Register (AQCSFRC), provided as an input to the PLECS block to allow dynamic register configuration.

The figure below shows the relevant cells of the register where CSFA and CSFB can be used to force an output. The following configurations are supported:

pict
AQCSFRC Register Configuration

As illustrated in the previous ePWM timing example, the change of an
ePWMx output lags the change of AQCSFRC by one counter clock period. Similar to the previously described registers with dynamic configuration, the AQCSFRC register is operated in shadow mode. The reload events can be defined with the AQSFRC register.

pict
AQSFRC Register Configuration

The supported modes for RLDCSF are listed below.

Immediate mode for loading is not supported due to implementation efficiency reasons.

Example Configuration - Step 2

The following figure shows an example using the actions defined by the AQCTLx registers. Refer to [4] for a detailed explanation of the action symbols.

[Picture]
Desired ePWMA and ePWMB output signals [4]

To realize the above ePWM signals, the dynamic configuration must be set as follows:

CMPA  = 3500;CMPB  = 2000;AQCSFRC  ,AQCTLA2   ,AQCTLB2   = 0

Furthermore, the Action-Qualifier must be set as shown below:

AQCTLA   = 18   ^=  0 0 0 0 0 0 0 0 0 0 0 1  0 0 1 0
                          ◟C◝B◜D◞◟C◝B◜◞U  ◟C◝A◜◞D ◟C◝◜A◞U  ◟P◝◜R◞D◟Z◝R◜O◞

AQCTLB   = 258  ^=  0 0 0 0 ◟0◝ 0◜◞0◟◝1◜◞ 0◟◝0◜◞ 0◟◝◜0◞ 0◟◝◜0◞◟1◝ 0◜◞
                          CBD CBU  CAD CAU  PRDZRO

Event-Trigger (ET) Submodule

This submodule utilizes the signals generated by the Time Base and Counter Compare submodules to generate events (pulses) at the ePWMSOCx outputs. Such pulses can trigger an ADC conversion or invoke the execution of a control algorithm or PIL block. For each ePWMSOC channel, the Event Trigger module provides an internal 4-bit counter which permits a downsampling of events. The following diagram shows the internal structure for the example of SOCA.

[Picture]
Event Trigger Logic [4]

As can be seen, the counter is being incremented using one of the source signals on the right-hand side.

The figures below show the structure of the ETPS and ETSOCPS registers.

pict
ETPS Register Configuration

pict
ETSOCPS Register Configuration

The SOCPSSEL bit determines whether SOCxCNT and SOCxPRD take control or whether SOCxCNT2 and SOCxPRD2, in the ETSOCPS register, take control.

The SOCxPRD and SOCxPRD2 bits determine the number of events that must occur before an SOCx pulse is generated. Refer to [4] for detailed information regarding the configuration of the ETPS and ETSOCPS registers.

The ETCNTINIT register is used to initialize the counter for the SOCA and SOCB events at startup. The structure of the register is shown below.

pict
ETSOCPS Register Configuration

The ETSEL register has the following structure.

pict
ETSEL Register Configuration

The SOCxEN bits activate or deactivate the SOCx pulses. The SOCxSEL cells determine the source for the event trigger counter. The SOCxSELCMP cells determine if CMPA and CMPB or CMPC and CMPD are used for SOCxSEL counter.

Note, SOCxSEL   = 000   is not supported in the model.

The incrementing source signal is selected by the SOCxSEL field and the SOCPSSEL bit determines which counter to use. An SOC pulse is generated when the SOC counter (SOCxCNT or SOCxCNT2) reaches its configurable period (SOCxPRD or SOCxPRD2) and pulse generation is activated by the SOCx flag. The configuration for both the SOCA and SOCB portion of the Event Trigger is set by the registers ETSEL, ETPS, ETSOCPS, and ETCNTINIT registers, which are realized as static parameters of the PLECS model.

Example Configuration - Step 3

A possible use case for the Event-Trigger submodule is to generate a SOCA pulse every second time the TB-counter meets the CMPA value. To achieve this behavior, the ET is configured as follows.

ETSEL  = 0xC00   ^=  0 0 0 0   1     1 0 0   0 0 0     0      0 0 0 0
                           SO◟C◝◜A◞EN SO◟C◝A◜S◞EL        SOCA◟S◝E◜L◞CMP

This setting enables the SOCA pulses and uses the CTR = CMPA event for incrementing the ET-counter. Note that SOCB pulses are completely disabled in this example.

ETPS   = 512   ^=  0 0 0 0 0 0 1 0    0 0    0    0  0 0 0 0
                            SOC◟A◝◜P◞RD       SOC◟P◝S◜◞SEL

Dead-Band Submodule

The role of this submodule is to add programmable delays to rising and falling edges of the ePWM signals and to generate signal pairs with configurable polarity. The figure below depicts the internal structure of the Dead-Band submodule.

[Picture]
Dead-Band Logic [4]

As shown, the PWMx signals from the Action-Qualifier submodule are post-processed based on the DBCTL register settings. Furthermore, the delay times are programmable by the registers DBRED and DBFED for the rising and falling edge delays, respectively. The structure of the DBCTL register is shown in the following block diagram.

pict
DBCTL Register Configuration

The submodule register cells allow for the following settings:

DBFED and DBRED are loaded to the active register from the shadow register on the events selected by LOADFEDMODE and LOADREDMODE bits, respectively. Only shadow mode operation is supported in the PLECS type 4 ePWM module.

In addition to the classic operation available on the type 1 ePWM module, the type 4 ePWM module provides additional operating modes. Refer to [4] for detailed information regarding the configuration of the DBCTL register and the additional operating modes.

[Picture]
Additional deadband operation modes [4]

Example Configuration - Step 4

In the sample configuration, the signal EPWMB is selected as the source for both delay counters. Further, both the rising and falling edges of the outputs are delayed by 10 counter clock periods and the polarities are not inverted. The DBCTL register therefore should be configured as follows.

DBCTL  = 0x0033 ^=  0 0 0 0 0 0 0 0 0 0 1 1  0 0      1 1
                                  INx◟M◝O◜D◞E  PO◟L◝x◜S◞EL OUT◟x◝◜M◞ODE

With the HALFCYCLE, DEDB_MODE, OUTSWAP, LOADFEDMODE, and LOADREDMODE bits set to zero, the DBRED and DBFED must be configured to:

DBRED  = 10 , DBFED   = 10

Analog Digital Converter (ADC) Type 2

The PLECS peripheral library provides two blocks for the TI ADC type 2 module, one with a register based configuration mask and a second with a graphical user interface. The figure below shows the register-based version of the PLECS type 2 ADC module.

pict
Register-based ADC module model

The register-based version allows the user to directly enter register values in decimal, binary, or hexadecimal notation. For convenience, the peripheral library also provides a component with a graphical user interface to simplify the configuration.

Both ADC blocks interface with other PLECS components over the following terminal groups:

ADC Module Overview

The PLECS ADC model implements the most relevant features of the MCU peripheral.

[Picture]
Overview of the type 2 ADC module in dual sequencer mode[2]

The ADC model implements the following features:

A section summarizing the differences of the PLECS type 2 ADC module as compared to the actual type 2 ADC module is provided in the Summary section.

ADC Converter with Result Registers

The type 2 ADC module contains a single 12-bit converter with dual sample-and-hold (S/H) circuits. The ADC can be configured to perform a series of conversions of preselected input channels each time a start-of-conversion (SOC) request is received. Once a conversion has completed, the result is stored in one of the 16 result registers, ADCRESULT0 - ADCRESULT15, as 12 bit unsigned integers. The content of the result registers is available at the output ports of the model.


Note  The Output Mode parameter allows the ADC results to be formatted as unsigned integers or quantized doubles.

[Picture]
ADC Core Clock and Sample-and-Hold Clock [2]

The period of the ADC clock, ADCCLK, and therefore the time base for the module, is determined based on the peripheral clock, HSPCLK, and is scaled down by the ADCCLKPS[3:0] bits of the ADCTRL3 register. An extra clock pre-scaler is provided with the CPS bit of the ADCTRL1 register.

The width of the sampling window in the ADC type 2 is controlled by the ACQ_PS[3:0] bits in the ADCTRL1 register. The ADC sampling time can be configured to be 1 - 8 cycles of the ADCCLK period. The figure above summarizes the scaling of the ADC Core Clock and the S/H clock.

ADC Sampling Mode

The ADC type 2 module can be configured to operate in sequential or simultaneous sampling mode. In the sequential sampling mode the two S/H circuits are operated independently. Any of the 16 input channels can be selected to be sampled by either of the two S/H circuits by configuring the appropriate register bit field CONVnn in the ADCCHSELSEQ1 - ADCCHSELSEQ4 registers. The table below summarizes the input channel configuration using the CONVnn bit field in sequential sampling mode.

CONVnnADC Input Channel Selected
0000ADCINA0
0001ADCINA1
......
0111ADCINA7
1000ADCINB0
......
1111ADCINB7

In simultaneous sampling mode, the S/H-A circuit can be configured to sample inputs ADCINA00 - ADCINA07 using the registers bit fields CONV00 - CONV07. In this sampling mode, the MSB of CONVnn is ignored. The S/H-B circuit will automatically sample the ADCINBnn input corresponding to the ADCINAnn input that is chosen. For example, if the CONVnn register contains the value 0110b, ADCINA6 is sampled by S/H-A and ADCINB6 is sampled by S/H-B. If the value is 1001b, ADCINA1 is sampled by S/H-A and ADCINB1 is sampled by S/H-B.

CONVnnInput pair
0000ADCINA0 / ADCINB0
0001ADCINA1 / ADCINB1
......
0111ADCINA7 / ADCINB7
1000ADCINA0 / ADCINB0
......
1111ADCINA7 / ADCINB7

The voltage in S/H-A is converted first, followed by the S/H-B voltage. The result of the S/H-A conversion is placed in the current ADCRESULTn register (e.g. ADCRESULT0). The result of the S/H-B conversion is placed in the next ADCRESULTn register (e.g. ADCRESULT1). The next conversion will be placed in the subsequent register (ADCRESULT2). The table above summarizes the input channel configuration given by CONVnn.

ADC Sequencer Mode

The ADC module consists of two 8-state sequencers (SEQ1 and SEQ2) that can be operated independently in dual-sequencing mode or can be combined to form one 16-state sequencer (SEQ1) in cascaded-sequencing mode. In dual-sequencing mode the maximum number of conversions for SEQ1 is set by MAX_CONV1[2:0] and SEQ2 by MAX_CONV2[2:0] bits in the ADCMAXCONV register. Cascaded-sequencing mode can be viewed as SEQ1 with 16 states instead of 8 where the maximum number of conversions is governed by MAX_CONV1[3:0] in the ADCMAXCONV register.


Note  In the PLECS ADC type 2 module, MAX_CONV1 and MAX_CONV2 are inputs that are sampled at SOC trigger events. Both inputs are sampled at trigger events ePWM_SOCA and ePWM_SOCB.

In the type 2 ADC, SOC requests received during an active sequence remain pending. Pending SOC requests are fulfilled as soon as the sequencer is initiated or immediately after an active sequence of conversions is finished. Additionally, in dual-sequencing mode, an SEQ1 conversion request is given higher priority over an SEQ2 conversion request. For example, assume that the converter is busy handling SEQ1 when an SOC request from SEQ2 occurs. The converter will start SEQ2 immediately after completing the active sequence of conversions. If another SOC conversion request from SEQ2 occurs before the active sequence of conversion is finished, this additional SOC request for SEQ2 is lost. However, if an SOC request for SEQ1 is received before the active sequence of conversion is finished, then both SOC requests from SEQ1 and SEQ2 will remain pending. When the current SEQ1 completes its active sequence, the SOC request for SEQ1 will be taken up immediately. The SOC request for SEQ2 will remain pending.

The CONVnn bit field in the ADCCHSELSEQ1 - ADCCHSELSEQ4 registers and the sampling mode, define the input pin to be sampled and converted for the result register ADCRESULTnn. For further details of the two different sampling modes and the conversion channel configuration, see section ADC Sampling Mode. The table below summarizes the sequencer differences in the two sequencer modes. Details of the SOC trigger configuration and the ADC interrupt configuration is discussed in section ADC Interrupt Logic.

FeatureSingle 8-state sequencer 1Single 8-state sequencer 2Cascaded 16-state sequencer
SOC triggersePWM SOCAePWM SOCBePWM SOCA, ePWM SOCB
Maximum number of auto conversions8816
Autostop at end-of-sequenceYesYesYes
Arbitration PriorityHighLowNot applicable
ADCCHSELSEQn bit field assignmentCONV00 to CONV07CONV00 to CONV07CONV00 to CONV15

In the PLECS ADC type 2 module, sequencer reset can be provided externally by the user. The inputs RST_SEQ1 and RST_SEQ2 are used to immediately reset the sequencers, SEQ1 and SEQ2, respectively. At a reset event, the ADC module will fulfill the request of any pending SOC request. If no SOC requests are pending the ADC module remains in idle mode until the next SOC trigger is received. For example, assume that the converter is busy handling SEQ1 with pending triggers for SEQ1 and SEQ2. If a sequencer 1 reset is received during the conversion, the active conversion is immediately stopped. After the reset, the converter is reinitialized by resetting the state pointer to CONV00 and the conversion result pointer to ADCRESULT0. Once the reinitialization process is completed, the pending SEQ1 trigger is cleared and the pending SEQ1 conversion is started. However, if a sequencer 2 reset is received during the conversion, the SEQ1 conversion is not stopped immediately. The sequencer 2 reset would ensure that the SEQ2 state pointer is reset to CONV08 and the conversion result pointer to ADCRESULT8 when the next SEQ2 conversion occurs.

Additionally, the PLECS ADC type 2 module can be configured to reset the sequencers internally at every or every other end-of-sequence. In this mode, the inputs RST_SEQ1 and RST_SEQ2 are ignored. The sequencer cannot be halted in mid sequence and must wait until an end-of-sequence (EOS) event for the next series of conversions to start. An internal reset event at every end-of-sequence would cause the state pointer to reset to CONV00 and the conversion result pointer to ADCRESULT0 for SEQ1 after one series of conversions. An internal reset event at every other end-of-sequence would cause the state pointer to reset to CONV00 and the conversion result pointer to ADCRESULT0 for SEQ1 after two series of conversions. After the first series of conversion is completed the state pointer and conversion result pointer are stored. The next set of conversions for SEQ1 will be started from the stored state pointer and conversion result pointer. For example, if the module is configured in simultaneous sampling mode with maximum number of conversions for SEQ1 set to two conversions, after the first series of conversions the state pointer points to CONV02 and the conversion result pointer to ADCRESULT4. The next conversion of SEQ1 will convert the channel selected in CONV02 and write the result into ADCRESULT4. At the end of the second series of conversions the state pointer is reset to CONV00 and the conversion result is reset to ADCRESULT0.

ADC Trigger and Interrupt Logic

The ADC control register, ADCTRL2, can be used to configure the SOC trigger pulses to start a sequence of conversions. In dual-sequencing mode, the ePWM_SOCB_SEQ2 bit is used to control the start of sequencing of SEQ2 by an ePWM_SOCB trigger.

The ePWM_SOCA_SEQ1 bit is used to control the start of sequencing of SEQ1 by an ePWM_SOCA signal for both dual-sequencing and cascaded-sequencing modes.

Additionally, in cascaded-sequencing mode the ePWM_SOCB_SEQ1 bit is used to control the start of sequencing of SEQ1 by an ePWM_SOCB signal (SEQ2 is unused in cascaded-sequencing mode).

After every sequence of conversions, the ADC generates an EOS pulse with the duration of one ADC clock period. The ADCTRL2 register can be used to configure the interrupts generated at the end of sequence of SEQ1 and SEQ2. The INT_ENA_SEQ1 and INT_ENA_SEQ2 bits are used to control the generation of an ADC interrupt signal for SEQ1 and SEQ2, respectively. With the register below, the interrupt behavior can be configured.

pict
ADC Control Register for ADC trigger and interrupt configuration [2]

The INT_ENA_SEQx bit enables the interrupt generation for SEQx.

The INT_MOD_SEQx bit configures the generation of an interrupt signal for SEQx at every EOS or every other EOS.

Summary of PLECS Implementation

The PLECS type 2 ADC module models the major functionality of the actual TI type 2 ADC module. Below is a summary of differences of the PLECS type 2 ADC module as compared to the actual type 2 ADC module:

Analog Digital Converter (ADC) Type 3

The PLECS peripheral library provides two blocks for the TI ADC type 3 module, one with a register based configuration mask and a second with a graphical user interface. The figure below shows the appearance of the block.

pict
ADC module model

The register-based version allows the user to directly enter register values in decimal, binary, or hexadecimal notation. For convenience, the peripheral library also provides a component with a graphical user interface to simplify the configuration.

Both ADC blocks interface with other PLECS components over the following terminal groups.

ADC Module Overview

The PLECS ADC model implements the most relevant features of the MCU peripheral.

[Picture]
Overview of the type 3 ADC module [1]

The ADC model implements these logical submodules:

ADC Converter with Result Registers

The type 3 ADC module contains a single 12-bit converter. Either an internal or an external voltage reference can be selected.

The converter takes 13   ADC clocks for a single conversion. The period of the ADC clock, and therefore the time base for the module, is determined based on the system clock and the two clock dividers specified in the ADCCTL2 register.

pict
ADCCTL2 Register structure

By using the bits CLKDIV4EN and CLKDIV2EN the ADC time base can be specified as follows.

CLKDIV2ENCLKDIV4ENADC clock
00SYSCLK
01SYSCLK
10SYSCLK / 2
11SYSCLK / 4

The bit ADCNONOVERLAP determines if an overlap of sampling and conversion is allowed in case of multiple pending conversion requests.

Once a conversion has completed, the result is stored to one of the 16 result registers ADCRESULT0 - ADCRESULT15. These are directly associated with the SOC. The content of the result registers is available at the output ports of the model. The representation of the conversion result can be chosen with the mask parameter Output Mode.

ADC Reference Voltage Generator

The ADC can use an internal or an external reference voltage. The internal bandgap range is [0V...3.3V], while the external reference can be specified in the component mask.

pict
ADCCTL1 Register structure

With the bit ADCREFSEL, the desired voltage reference can be chosen.

The component only supports the late interrupt pulse mode. Therefore the bit INTPULSEPOS should be one.

ADC Sample Generation Logic

The ADC Sample Generation Logic responds to the SOCx signals, which are based on 16 individual sets of configuration parameters SOC0 - SOC15. Every SOC contains the following information:

The register used for configuring a SOC is shown below.

pict
ADCSOCxCTL Register structure

The register cell ACQPS defines the length of the sampling window. The minimum value valid is 06h   which sets the Sample Window to 6+1 ADC clock cycles. Note according to the hardware documentation, there are a number of invalid settings for this register field:

10 , 11 , 12 , 13 , 14 , 1D , 1E , 1F , 20 , 21 , 2A , 2B  , 2C
  h    h    h   h    h     h    h    h    h   h     h    h    h

2Dh , 2Eh , 37h , 38h , 39h , 3Ah , 3Bh

The time needed for a full conversion can be calculated with the following equation.

Tconv = (ACQPS + 1)⋅ADCclk + 13⋅ADC  clk
      ◟--------◝◜--------◞  ◟---◝◜---◞
          SamplingWindow       Conversion

The CHSEL field associates an input pin with a specific SOC. The component allows single and simultaneous sampling - see section ADC Input Circuit. For a SOC in single sample mode, cell configuration is as follows.

CHSELInput
0hADCINA0
1hADCINA1
......
7hADCINA7
8hADCINB0
......
FhADCINB7

In case of simultaneous sample mode, the channel selection is configured as pairs.

CHSELInput pair
0hADCINA0 / ADCINB0
1hADCINA1 / ADCINB1
......
7hADCINA7 / ADCINB7
> 7hInvalid Selection

With the TRIGSEL field it is possible to choose a particular trigger source available as a block input. The PLECS component only supports ePWMx_SOCy trigger signals. The following table shows the mapping to the hexadecimal representation. Configurations above 14
  h   and below 05
  h   are invalid and result in an error.

TRIGSELInput / Source
05hePWM1_SOCA
06hePWM1_SOCB
07hePWM2_SOCA
......
14hePWM8_SOCB

Additionally, it is possible to configure the interrupt signals INT1 and INT2 to trigger ADC conversions. See section ADC Interrupt Logic for further details.

During operation of an ADC, more than one conversion trigger can occur simultaneously. A SOC can also be triggered while a conversion is already active. A round robin method prioritizes pending SOCs. This scheme is accurately reflected by the PLECS component. The figure below shows an example snapshot of the round robin wheel.

[Picture]
ADC Prioritization example [1]

This wheel consist of 16 SOC flags and a round robin pointer (RRPOINTER). A SOC flag is set when a trigger is received and is cleared when the corresponding conversion finishes. The round robin pointer always points to the last converted SOC and is changed with the end of every conversion. In the PLECS ADC model, the round robin pointer initially points to SOC15. In the example above, the round robin pointer points to SOC7 indicating this is the last converted SOC. At this point in time, the SOC2 and SOC12 are triggered and the corresponding flags are set. For prioritization, the ADC starts with RRPOINTER+1 and goes clockwise through the round robin wheel, meaning SOC12 is executed next in this example.

The hardware ADC also provides higher prioritized SOCs and a ONESHOT single conversion mode. These are not supported by the PLECS model.

ADC Input Circuit

The Input Circuit of the type 3 ADC module consists of two separate Sample&Hold circuits (S&H), each connected to a multiplexer. The field CHSEL from the ADCSOCxCTL register associates an input with a particular SOC. Measurements of TEMP SENSOR and VREFLO are not supported by the PLECS model. The figure below shows the hardware circuit schematic of an ADCIN voltage connected to an S&H circuit.

[Picture]
ADCInx Input Model [1]

After an SOC is triggered from the round robin wheel, the switch is closed for the sampling window changing the voltage of the sampling Capacitor Ch  . Once the sampling time has elapsed, the switch is opened and the conversion starts. For simulation efficiency reasons, the PLECS model of the ADC approximates this behavior by taking the average of the input values at the begin and end of the sampling window.

The type 3 ADC further provides single as well as simultaneous measurements. For a single measurement, only one S&H circuit is active at a time. For simultaneous measurements, both S&H circuits operate in parallel, sampling two different voltages at the same time. The conversion is carried out sequentially starting with the upper S&H voltage. The sampling mode is assigned pairwise, always in groups of even and odd SOCs using the register shown below.

pict
ADCSAMPLEMODE Register structure

With the bit SIMULENx, the sampling mode can be chosen as follows.

In case of simultaneous mode, both SOCs can still be configured independently by the ADCSOCxCTL registers. The behavior during conversion (sample window length and channel selection) is always determined by the triggered SOC. For a more advanced understanding of the modules behavior and configuration, please refer to [1].

ADC Interrupt Logic

For every conversion, the ADC sample generation logic generates an end of conversion pulse (EOC) with duration one ADC clock period. This pulse is generated one cycle before latching the conversion result. The interrupt pulse always lags the EOC pulse by one ADC clock period and therefore is simultaneous to the result latch. The ADC Interrupt Logic can generate the interrupts ADCINT1-ADCINT9, which are available at the output ports of the ADC model. With the register below, the interrupt behavior can be configured.

pict
INTSELxNy Register structure for the example of INT1 and INT2

The INTxE bit enables the interrupt generation by an EOC flag.

The INTxSEL cell defines which EOC flag triggers the interrupt.

INTxSELInterrupt Trigger
00hEOC0 triggers interrupt ADCINTx
01hEOC1 triggers interrupt ADCINTx
......
0fhEOC15 triggers interrupt ADCINTx
> 0fhInvalid Selection


Note  The cells INT10E and INT10SEL in INTSEL9N10 have no effect because the model only supports the interrupts ADCINT1-ADCINT9.
Additionally, the interrupts INT1 and INT2 can be configured to internally trigger SOCs, using the the following registers:

pict
ADCINTSOCSEL1 Register structure

pict
ADCINTSOCSEL2 Register structure

The field SOCx can be configured as follows.

SOCxInterrupt Trigger
00No ADCINT will trigger SOCx
01ADCINT1 will trigger SOCx
10ADCINT2 will trigger SOCx
11Invalid Selection

The setting in this register, if not 00  , overwrites the trigger setting defined in the field TRIGSEL of the ADCSOCCTLx register.

Analog Digital Converter (ADC) Type 4

The PLECS peripheral library provides two blocks for the TI ADC type 4 module, one with a register based configuration mask and a second with a graphical user interface. The figure below shows the appearance of the block.

pict
ADC module model

The register-based version allows the user to directly enter register values in decimal, binary, or hexadecimal notation. For convenience, the peripheral library also provides a component with a graphical user interface to simplify the configuration.

Both ADC blocks interface with other PLECS components over the following terminal groups.

ADC Module Overview

The PLECS ADC model implements the most relevant features of the MCU peripheral.

pict

Overview of the type 4 ADC module [4]

The ADC model implements these logical submodules:

ADC Converter and Result Register

The type 4 ADC module contains a single converter with an external voltage reference specified in the component mask. It supports 12-bit and 16-bit resolution and can be operated in single-ended or differential mode depending on the settings in the ADCCTL2 register.

pict
ADCCTL2 Register structure

The bits SIGNALMODE and RESOLUTION determine the behavior and the resolution used by the ADC. Please note that only the following combinations are valid:

SIGNALMODE/RESOLUTION12-bit (0)16-bit (1)
Single-Ended (0)x
Differential (1)x

The converter takes 29.5   (16-bit) or 10.5   (12-bit) ADC clocks for a single conversion. The period of the ADC clock is derived from the system clock, specified in the component mask, and the PRESCALE bit specified in the ADCCTL2 register.

PRESCALEADC Clock
0hADCCLK = System Clock / 1.0
1hInvalid
2hADCCLK = System Clock / 2.0
3hADCCLK = System Clock / 2.5
4hADCCLK = System Clock / 3.0
......
FhADCCLK = System Clock / 8.5

Once a conversion has completed, the result is stored to one of the 16 result registers ADCRESULT0 - ADCRESULT15. These are directly associated with the SOC. The content of the result registers is available at the output ports of the model. The representation of the conversion result can be chosen with the mask parameter Output Mode.

ADC SOC Arbitration & Control

The ADC Arbitration Logic is defined by SOCx configurations, which consist of 16 individual sets of configuration parameters SOC0 - SOC15. Every SOC contains the following information:

The register used for configuring a SOC is shown below.

pict
ADCSOCxCTL Register structure

The register cell ACQPS defines the length of the sampling window. The sampling window is determined by the system clock and needs to be chosen to last at least one ADC clock period.

The time needed for a full single ended conversion can be calculated as follows.

Tconvxsingle- ended = (◟ACQPS-+◝◜1)⋅SYSclk◞+ 1◟0.5-⋅A◝D◜C-clk◞
                    SamplingWindow        Conversion

For a differential conversion, the time needed is determined by

Tconvxdifferential = (ACQPS + 1)⋅SYSclk+ 29.5 ⋅ADC clk
               ◟--------◝◜-------◞  ◟----◝◜----◞
                   SamplingWindow        Conversion

The CHSEL field associates an input (single-ended mode) or a pair of inputs (differential mode) with a specific SOC. For more details, see section ADC Input Circuit. In single-ended mode, the input configuration for a SOC is as follows.

CHSELInput
0hADCIN0
1hADCIN1
......
FhADCIN15

In case of differential mode, the channel selection is configured as pairs.

CHSELInput pair
0hADCIN0 / ADCIN1
1hADCIN0 / ADCIN1
2hADCIN2 / ADCIN3
3hADCIN2 / ADCIN3
......
EhADCIN14 / ADCIN15
FhADCIN14 / ADCIN15

With the TRIGSEL field it is possible to choose a particular trigger source available as a block input. The ADC model only supports ePWMx_SOCy/z trigger signals. The following table shows the mapping to the hexadecimal representation. Configurations above 1Ch   and below 05h   are invalid and result in an error.

TRIGSELInput / Source
05hePWM1_SOCA/C
06hePWM1_SOCB/D
07hePWM2_SOCA/C
08hePWM2_SOCB/D
......
1BhePWM12_SOCA/C
1ChePWM12_SOCB/D

Additionally, it is possible to configure the interrupt signals INT1 and INT2 to trigger ADC conversions. See section ADC Interrupt Logic for further details.

During operation of an ADC, more than one conversion trigger can occur simultaneously. A SOC can also be triggered while a conversion is already active. A round robin method prioritizes pending SOCs. This scheme is accurately reflected by the PLECS component. The figure below shows an example snapshot of the round robin wheel.

[Picture]
ADC Prioritization example [4]

This wheel consist of 16 SOC flags and a round robin pointer (RRPOINTER). A SOC flag is set when a trigger is received and is cleared when the corresponding conversion finishes. The round robin pointer always points to the last converted SOC and is changed with the end of every conversion. In the PLECS ADC model, the round robin pointer initially points to SOC15. In the example above, the round robin pointer points to SOC7 indicating this is the last converted SOC. At this point in time, the SOC2 and SOC12 are triggered and the corresponding flags are set. For prioritization, the ADC starts with RRPOINTER+1 and goes clockwise through the round robin wheel, meaning SOC12 is executed next in this example.

The hardware ADC also provides higher prioritized SOCs, software triggering and a burst mode. These are not supported by the PLECS model.

ADC Input Circuit

The Input Circuit of the type 4 ADC module consists of a single Sample&Hold circuit (S&H) connected to a multiplexer.

In single-ended mode, a single input is connected to the S&H circuit as shown below.

[Picture]
ADCInx Input Model in Single-Ended Mode [4]

In this mode, a single input voltage is converted with 12bit resolution. The ADC operates in range [VREFLO ... VREFHI]. The reference voltage can be specified in the component mask.

In differential mode, the difference between two voltages can be measured with 16-bit resolution.

[Picture]
ADCInx Input Model in Differential Mode [4]

In this mode, the ADC operates in range [-VREFHI ... VREFHI].

The field CHSEL from the ADCSOCxCTL register associates an input or a pair of inputs with a particular SOC.

After an SOC is triggered from the round robin wheel, the switch is closed for the sampling window changing the voltage of the sampling Capacitor Ch  . Once the sampling time has elapsed, the switch is opened and the conversion starts. For simulation efficiency reasons, the PLECS model of the ADC approximates this behavior by taking the average of the input values at the begin and end of the sampling window.

The behavior during conversion (sample window length and channel selection) is always determined by the triggered SOC. For a more advanced understanding of the modules behavior and configuration, please refer to [4].

ADC Interrupt Logic

For every conversion, the SOC Arbiter logic generates an end of conversion pulse (EOC). This pulse results in an interrupt pulse with duration of one system clock. The component only supports the late interrupt pulse mode. Therefore the bit INTPULSEPOS in the ADCCTL1 register needs to be set to one.

pict
ADCCTL1Register structure

Based on this, the interrupt pulses always occur synchronous to latching the conversion results to the output.

The ADC Interrupt Logic can generate the interrupts ADCINT1-ADCINT4, which are available at the output ports of the ADC model. With the register below, the interrupt behavior for INT1 and INT2 can be configured.

pict
ADCINTSELxNy Register structure for the example of INT1 and INT2

In the model, the Interrupt Logic can only be operated in Continuous Mode. Therefore, the bit INTxCONT always needs to be set.

The INTxE bit enables the interrupt generation by an EOC flag.

The INTxSEL cell defines which EOC flag triggers the interrupt.

INTxSELInterrupt Trigger
0hEOC0 triggers interrupt ADCINTx
1hEOC1 triggers interrupt ADCINTx
......
fhEOC15 triggers interrupt ADCINTx

Additionally, the interrupts INT1 and INT2 can be configured to internally trigger SOCs, using the the following registers:

pict
ADCINTSOCSEL1 Register structure

pict
ADCINTSOCSEL2 Register structure

SOCxInterrupt Trigger
00No ADCINT will trigger SOCx
01ADCINT1 will trigger SOCx
10ADCINT2 will trigger SOCx
11Invalid Selection

The setting in this register, if not 00  , overwrites the trigger setting defined in the field TRIGSEL of the ADCSOCCTLx register.

Post-Processing Blocks

The type 4 ADC module contains four PPB blocks to post-process the conversion results. The figure below shows the block diagram of a single submodule.

pict

Overview of the type 4 ADC PPB submodule [4]

The PPB blocks add the following features to the ADC.

Each PPB block is associated to a single SOC. This can be configured with the register ADCPPBxCONFIG shown below.

pict
ADCPPBxCONFIG Register structure

The field CONFIG determines the associated SOC.

CONFIGSOC
0hSOC0
1hSOC1
......
FhSOC15

Note that multiple PPB blocks can point to a single SOC. The default used is SOC0.

The PPB block implements an offset correction for the conversion result of the associated SOC. The result of this calculation is presented at the ADCRESULTx output. The calculation further saturates at 0 at the low end and either 4095 or 65535 at the high end, depending on the signal mode (single-ended or differential). The offset can either be positive or negative and is defined by the ADCPPBxOFFCAL register shown below.

pict
ADCPPBxOFFCAL Register structure

The field OFFCAL defines the offset used.

OFFCALOFFSET
0h-1
1h-2
......
1FFh-512
200h+512
......
3FEh+2
3FFh+1


Note  If multiple PPB's are associated to an SOC, the ADCPPBxOFFCAL register of the PPB with the highest ID is used for the calculation.

In addition to the offset calculation, the PPB implements an error calculation depending on the field TWOSCOMPEN in the PPBxCONFIG register and the ADCPPBxOFFREF input.

The result of this calculation produces a sign extended integer result and is available at the ADCPPBxRESULT output.

The PPB block further implements a Zero-Crossing- and Limit-Detection for the PPB results. The Limits compared to the ADCPPBxRESULT registers are specified with the trip registers shown below.

pict
ADCPPBxTRIPHI Register structure for differential mode (16-bit)

pict
ADCPPBxTRIPLO Register structure for differential mode (16-bit)

pict
ADCPPBxTRIPHI Register structure for single-ended mode (12-bit)

pict
ADCPPBxTRIPLO Register structure for single-ended mode (12-bit)

Please note that the bits used within those registers depend on the signal mode. For the registers ADCPPBxRESULT, ADCPPBxTRIPLO and ADCPPBxTRIPHI, the bit usage is indicated below.

SIGNALMODESign bitData bits
0 - single-ended12 [11:0]
1 - differential 16 [15:0]

The information from the Zero-Crossing- and Limit-Detection is stored within the ADCEVTSTAT register.

pict
ADCEVTSTAT Register structure

This register is shared by all PPB blocks and is available at the model output. The status can further be used to generate ADC-Events and/or ADC-Interrupts. The state changes resulting in events and interrupts are configured using the ADCEVTSEL and ADCINTEVTSEL registers in the mask.

pict
ADCEVTSEL Register structure

pict
ADCINTEVTSEL Register structure

While every PPB hast its own ADCEVTx output, all PPBs share one interrupt flag available at the ADCEVTINT output.

Each PPB further provides a functionality to capture the delay between a trigger to the associated SOC and the effective start of the conversion. This information is provided as multiples of the used system clock period and stored in the ADCPPBxSTAMP register.

pict
ADCPPBxSTAMP Register structure


Note  The DLYSTAMP is calculated based on a 12-bit counter and wraps around at 4095.

Enhanced Capture (eCAP) Type 0

The PLECS peripheral library provides two blocks for the TI eCAP Type 0 module operated in capture mode: one with a register based configuration mask and a second with a graphical user interface (GUI). The peripheral library also includes a block for the TI eCAP Type 0 module operated in APWM mode. The figure below shows the GUI-based version of the PLECS Type 0 eCAP module operated in capture mode and the PLECS Type 0 eCAP module operated in APWM mode.

pict
PLECS eCAP modules operated in APWM and Capture modes

The register-based version allows the user to directly enter register values in decimal, binary, or hexadecimal notation. For convenience, the peripheral library also provides a component with a GUI to simplify the configuration.

The PLECS eCAP models implement the most relevant features of the MCU peripheral.

eCAP Module Operated in Capture Mode

When operated in capture mode, the eCAP module interfaces with other PLECS components over the following terminal groups:

[Picture]
Overview of the type 0 eCAP module in capture mode [3]

The eCAP model operated in capture mode implements the following features:

Event Prescaler

The event prescaler bits ECCTL1[13:9] can be used to reduce the frequency of the input capture signal. When a prescale value of 1 is chosen (i.e., ECCTL1[13:9] = 0,0,0,0,0) the input capture signal bypasses the prescale logic completely. Alternatively, the prescaler can be scaled by a factor of 2 to 62 using the ECCTL1[13:9] bits. This is useful when very high frequency signals are used as inputs.

pict
Event prescaler control [3]

Edge Polarity Select and Capture Control

Independent edge polarities can be selected for each of the 32-bit CAP1-4 registers to capture the counter value. Loading of the capture registers can be disabled by clearing the CAPLDEN bits in the ECCTL1 register. The bits CAPxPOL in the ECCTL1 are used to configure the CAPx capture event on a rising or falling edge.

The PLECS eCAP module can only be operated in continuous capture control mode. A 2-bit counter continues to run (0->1->2->3->0) and capture values continue to be written to CAP1-4 in a circular buffer sequence. The CTRRST1-4 bits in the ECCTL1 register can be used to force the counter to reset after a capture event. This is useful when the eCAP module is operated in difference mode.

The STOP_WRAP bits in the ECCTL2 register can be used to program the 2-bit counter wrapping to occur after any of the four capture events.


Note  The PLECS eCAP module does not support One-Shot capture control mode.

eCAP Module Operated in APWM Mode

When operated in APWM mode, the eCAP module interfaces with other PLECS components over the following terminal groups:

[Picture]
PWM waveform details of eCAP module operated in APWM mode [3]

The PLECS APWM mode supports shadow mode operation only. The CAP3-4 register values are transferred to their active register on a period event. The CAP3 input corresponds to writing to the period shadow register and the CAP4 input corresponds to writing to the compare shadow register.


Note  Immediate update operation in APWM mode is not supported.

eCAP Interrupts

In capture mode, the eCAP module can be configured to generate an interrupt at any of the 4 capture events using the CEVTx bits in the ECEINT register.

In APWM mode, the eCAP module can be configured to generate an interrupt at counter equals period and counter equals compare events. This can be done by setting the CTR=PRD and CTR=CMP bits in the ECEINT register, respectively.

In both modes, a counter overflow event (FFFFFFFF->00000000) can be configured to produce an interrupt by configuring the CTROVF bit in the ECEINT register.


Note  Flags used to generate the interrupt signal are automatically cleared in the PLECS eCAP module after one system clock period for ease of use.

eCAP Counter Update

The PLECS eCAP module provides users access to the 32-bit counter as a probe signal. To improve simulation efficiency the counter value is not sampled every system clock period. Instead, the user defines a counter sampling frequency to sample the counter value at the desired frequency.


Note  Higher counter sampling frequency increases counter resolution but reduces simulation speed.

Summary of PLECS Implementation

The PLECS eCAP module models the major functionality of the actual TI type 0 eCAP module. Below is a summary of the differences between the PLECS Type 0 eCAP module and the actual Type 0 eCAP module:

Reference

1 - Pictures provided with Courtesy of Texas Instruments, Literature source: TMS320x2806x Piccolo Technical Reference Manual, Literature Number SPRUH18D, January 2011-February 2013
2 - Pictures provided with Courtesy of Texas Instruments, Literature source: TMS320x2833x Analog-to-Digital Converter (ADC) Module Reference Guide, Literature Number SPRU812A, September 2007 - Revised October 2007
3 - Pictures provided with Courtesy of Texas Instruments, Literature source: TMS320x2833x, 2823x Enhanced Capture (eCAP) Module Reference Guide, Literature Number: SPRUFG4A, August 2008 - Revised June 2009
4 - Pictures provided with Courtesy of Texas Instruments, Literature source: TMS320x2837xD, 2827xD Analog-to-Digital Converter (ADC) Module Reference Guide, Literature Number: SPRUHM8C, December 2013 - Revised December 2014