Microchip dsPIC33F Peripheral Models
Introduction
Microcontrollers (MCUs) for control applications typically contain peripheral modules such as Analog-to-Digital Converters (ADCs) and pulse width modulators (PWMs). These peripherals play an important role, since they act as the interface between the digital/analog signals of the control hardware and the control algorithms running on the processor. State-of-the-art MCUs often include peripherals with a multitude of advanced features and configurations to help implement complex sampling and modulation techniques.
When modeling power converters in a circuit simulator such as PLECS, it is desirable to represent the behavior of the MCU peripherals as accurately as possible. Basic Sample&Hold blocks and PWM modulators are useful for higher-level modeling. However, important details with regards to timing and quantization are lost when attempting to model an ADC with a basic zero-order hold (ZOH) block. For example, employing an idealized modulator to generate PWM signals can result in simulation results substantially different from the real hardware behavior.
Accurate peripheral models are even more important in the context of Processor-In-the-Loop (PIL) simulations. In this case, it is imperative to utilize peripheral models which are configurable exactly as the real implementations, i.e. by setting values in peripheral registers. By the same token, the inputs and outputs of the peripheral models must correspond precisely to the numerical representation in the embedded code.
The PLECS PIL library includes high-fidelity MCU peripheral models which work at the register level, and are therefore well-suited for PIL simulations. Furthermore, certain blocks have a second implementation with a graphical user interface (GUI) that automatically determines the register configurations based on text-based parameter selections.
Subsequent sections describe the PLECS peripheral components in detail and highlight modeling assumptions and limitations. When documenting peripheral register settings, the following color coding is used:
- Grey (dark shading): No effect on the model behavior
- Green (light shading): Register cell affects the behavior of the model
Microchip Motor Control PWM
The PLECS peripheral library provides two blocks for the Microchip Motor Control PWM (MCPWM) module, one with a register-based configuration mask and a second with a graphical user interface. The figure below shows the register-based version of the MCPWM module.
Register-based MCPWM module model
The register-based version allows the user to directly enter register values in decimal, binary, or hexadecimal notation. For convenience, the peripheral library also provides a component with a graphical user interface to simplify the configuration.
Both MCPWM blocks interface with other PLECS components over the following terminal groups:
- PDCx - input ports for duty cycle register
- PSECMP - input port for special event trigger compare register
- PWMIF - output port for PWM interrupt flag
- SEVT - output port for special event trigger
- PWMHx/Lx - output ports for PWM signals
Note In the PLECS MCPWM module, PWM Faults and PWM Output Override have not been modeled
MCPWM Module Overview
The PLECS MCPWM model implements the most relevant features of the MCU peripheral.
Overview of the MCPWM module[1]
The MCPWM model implements the following features:
- PWM Clock Control
- PWM Output Control and Resolution
- Interrupt Control
- Special Event Trigger
- Dead Time Generator
A section summarizing the differences of the PLECS MCPWM module as compared to the actual MCPWM module is provided in the Summary section.
PWM Clock Control
The modeled MCPWM realizes a counter that can operate in three different modes for the generation of asymmetrical and symmetrical PWM signals. The three supported modes are:
- Free Running mode
- Continuous Up/Down mode
- Continuous Up/Down mode with interrupts for double PWM updates
The counter for these modes is visualized below.
Counter modes [1]
In Free Running mode, the counter is incremented from to a counter period
PTPER using a counter clock operated at a clock frequency of
. The PTPER
value corresponding to a desired PWM frequency (
) can be calculated
as:
When the counter reaches the period (PTPER), the subsequent count value is reset to zero, duty cycle (PDCx) and special event (PSECMP) registers are updated, and the sequence is repeated.
In the Continuous Up/Down mode, and Continuous Up/Down mode
with interrupts for double PWM updates, the counter is incremented from
to a counter period PTPER and then decremented back to
using a
counter clock operated at a clock frequency of
. The PTPER value
corresponding to a desired PWM frequency (
) can be calculated
as:
In the Continuous Up/Down mode, when the counter reaches , the duty cycle
(PDCx) and special event (PSECMP) registers are updated.
In the Continuous Up/Down mode with interrupts for double PWM updates, the
duty cycle (PDCx) and special event (PSECMP) registers are updated when the
counter reaches and PTPER.
Note In the PLECS MCPWM module, Single Event Mode is not allowed.
While the system clock and the period counter value are separately defined in the mask parameters, the counter mode and the clock divider are jointly configured in the PTCON register.
PTCON Register Configuration [1]
The input clock () derived from the oscillator source can be prescaled using
the PTCKPS bits in the PTCON register. Additionally, the counter mode selected
using the PTMOD bits and the time-based output post scalar (PTOPS) bits
determine the generation of the PWM interrupt flag.
Example Configuration - Step 1
This example shows the configuration of the PWM module operating in Free
Running mode with a 50 period. The PTCON register is configured
to:
According to this configuration, the time-based submodule is operating in the
Free Running mode with a timer clock period four times the system clock period. For
a PTPER value of and an
MHz system clock, the resulting PWM signal
has the following period:
PWM Output Control and Resolution
The MCPWM model for a non-zero duty cycle results in outputs of the PWM generators to be driven active at the beginning of the PWM period. Each PWM output will be driven inactive when the value of the counter matches the duty cycle value of the PWM generator. If the value of the duty cycle register is zero, the output on the corresponding PWM pin is inactive for the entire PWM period. The PWM output is active for the entire period if the value of PDC is greater than PTPER.
Note In the implemented model, immediate update of the PDC and PSECMP registers is not modeled.
FPOR:POR Register Configuration [1]
The HPOL and LPOL bits in the FPOR:POR register determine the output polarity of the high-side and low-side output pins of the PWM generators. For example, if the LPOL bit is set, then the low-side output is high when the PWM is active and low when the PWM is inactive. If the bit is cleared, then the low-side output is low when the PWM is active and high when the PWM is inactive.
PWMCON1 Register Configuration [1]
In the MCPWM, each PWM generator can be operated in either complementary or independent mode. In complementary mode both output pins cannot be active simultaneously. Additionally, a dead time is inserted during device switching making both outputs inactive for a short period. In independent mode there are no restrictions on the state of the pins for a given output pin pair. Additionally, the dead time module is disabled when the PWM module is operated in independent mode. The mode for each of the PWM generators is selected by configuring the bits PMOD4:PMOD1 in the PWMCON1 register.
The first bit of the register PDC determines whether the PWM signal edge occurs
at the or
boundary. The figure below illustrates the effect of this bit on
the PWM output.
Duty cycle resolution timing diagram, Free Running mode, and 1:1 prescaler selection
[1]
Special Event Trigger
The MCPWM can be configured to trigger the Analog-to-Digital (ADC) converter using the special event compare register (PSECMP). This allows ADC sampling and conversion timing to be synchronized to the PWM time base and provides the flexibility of programming the start of conversion at any point within the PWM period.
PSECMP Register Configuration [1]
The PWM counter register is compared to the SEVTCMP bits in the PSECMP register and generates a trigger signal when the counter value is equal to the SEVTCMP bits. In Up/Down Count mode, the SEVTDIR bit provides added flexibility on the generation of the trigger signal. When this bit is set, the trigger is generated on a match event when the counter is counting down. When the bit is set to zero, the trigger is generated on a match event when the counter is counting up.
Additionally, the Special Event Trigger Postscaler (SEVOPS) bits in the PWMCON2 register allows a 1:1 to 1:16 post scale ratio. These bits can be configured if the ADC conversions are not required every PWM cycle.
PWMCON2 Register Configuration [1]
Interrupt Control
The MCPWM module can be configured to generate an interrupt flag depending on the mode of operation and the time base postscaler (PTOPS) bits in the PTCON register. In the model the interrupt flag (PWMIF) is internally reset automatically after one simulation step.
In the Continuous Up/Down mode with interrupts for double PWM updates, an
interrupt event is generated each time the counter equals and PTPER. The
postscaler selection bits are ignored in this mode.
In the Free Running mode the interrupt flag is generated when the counter is
reset to . In the Continuous Up/Down mode, the interrupt flag is generated when
the counter is equal to
and the counter is counting up. In both of these
modes, the postscaler bits can be used to reduce the frequency of interrupt
events.
Dead Time Generator
In independent mode, the dead-time module is inactive and no dead-time is inserted between the high-side and low-side PWM signals of a PWM output generator. When operated in complementary mode, each PWM output generator can be configured to have some dead time between the turn on and turn off of the high-side and low-side PWM signals.
Dead time insertion [1]
The Dead Time Control Register 1 (PDCTON1) is used to configure two different
dead-time units (Unit A and Unit B). The DTA bits are used to assign a 6-bit
dead-time value for Unit A. The DTAPS bit is used to configure the dead-time clock
as a multiple of the system clock (). The corresponding bits DTB and DTBPS
are used to configure Unit B.
PDTCON1 Register Configuration [1]
The dead-time for Unit A and Unit B, are calculated as follows:
where refers to Unit A or B.
The Dead Time Control Register 2 (PDCTON2) contains configuration bits that are used to control the insertion of dead time when the high-side or low-side PWM signals become active. The DTS1I - DTS4I bits select the dead time inserted before PWML1 - PWML4, respectively, are driven active. The DTS1A - DTS4A bits select the dead time inserted before PWMH1 - PWMH4, respectively, are driven active.
PDTCON2 Register Configuration [1]
Summary of PLECS Implementation
The PLECS MCPWM module models the major functionality of the actual MCPWM module. Below is a summary of differences of the PLECS MCPWM module compared to the actual MCPWM module:
- PWM Faults and PWM Output Override are not supported.
- Single Event Mode is not supported.
- Immediate update of the PDC and PSECMP registers is not supported.
- PWM update lockout is not supported.
- The interrupt flag (PWMIF) is internally reset automatically after one simulation step.
Microchip Motor Control ADC
The PLECS peripheral library provides two blocks for the Microchip Motor Control ADC (MCADC) module, one with a register-based configuration mask and a second with a graphical user interface. The figure below shows the appearance of the register-based version.
Register-based MCADC module model
The register-based version allows the user to directly enter register values in decimal, binary, or hexadecimal notation. For convenience, the peripheral library also provides a component with a graphical user interface to simplify the configuration.
Both MCADC blocks interface with other PLECS components over the following terminal groups:
- ANx - input ports for duty cycle register
- Triggers - input port for INT0, Timer, and PWM triggers
- ADCBUFx - output port for ADC buffer register
- ADIF - output port for ADC interrupt flag
Note In the PLECS MCADC module, the GP timer triggers (Timer 3 and Timer 5) and Motor Control PWM 1 and 2 triggers have been lumped into a single Timer and PWM trigger, respectively.
MCADC Module Overview
The PLECS MCADC model implements the most relevant features of the MCU peripheral.
Overview of the MCADC module without DMA [2]
The MCADC model implements the following features:
- ADC Configuration
- ADC Sampling and Conversion
- Multi-channel ADC Sampling Mode
- ADC Input Selection Mode
- ADC Interrupt Logic
- ADC Buffer Fill Mode
A section summarizing the limitation of the PLECS MCADC module as compared to the actual MCADC module is provided in the Summary section.
ADC Configuration
The MCADC module can be operated either in 10-bit or 12-bit operation mode. The 12-bit Operation Mode bit (AD12B) in the ADCON1 register allows the ADC module to function as either a 10-bit, 4-channel ADC (when the AD12B bit is cleared) or a 12-bit, single-channel ADC (when the AD12B bit is set). In 10-bit mode, the CHPS bits in the ADCON2 register can be configured to operate the MCADC module to convert:
- only
and
,
,
, and
The VCFG bits in the ADCON2 register allow the selection of the voltage
references for the MCADC module. The voltage reference high () and the
voltage reference low (
) for the ADC module can be supplied from the
internal
and
voltage rails or the external
and
input pins. The table below summarizes the different configurations that are possible
by setting the VCFG bits.
VCFG | VREFH | VREFL |
000 | AVDD | AVSS |
001 | VREF+ | AVSS |
010 | AVDD | VREF- |
011 | VREF+ | VREF- |
1xx | AVDD | AVSS |
The MCADC module clock () can be configured to use the system clock
(
) or a dedicated internal RC clock (
). The figure below summarizes
the generation of the ADC clock.
ADC Clock Generation [2]
While the system clock and the period counter value are separately defined in the mask parameters, the ADC clock source selection (ADRC) and the clock divider (ADCS) are jointly configured in the ADCON3 register.
ADCON3 Register Configuration [2]
The clock divider is used to lower the frequency when the ADC clock is derived from the system clock. The ADCS bits allow the clock to be scaled to one of 64 settings, from 1:1 to 1:64. The table below summarizes the effect the ADCS and ADRC bits have on the ADC clock period.
ADRC | ADC Clock Period (TAD) |
0 | TCY · (ADCS + 1) |
1 | TADRC |
Note ADCS values over 63 are reserved in the actual hardware and will be flagged as an error in the PLECS MCADC module.
The MCADC module can be configured to output the ADC results in four different numerical formats. The FORM bits in the ADCON1 register select the data format. Further, in the PLECS MCADC module the output format can be configured as quantized double format for convenience. The Output mode block parameter selects if the FORM bits are used or if the output is presented as a quantized double format. The table below summarizes the different available formats.
FORM | Output Mode | Data Format |
00 | Use FORM bits | Unsigned Integer |
01 | Use FORM bits | Signed Integer |
10 | Use FORM bits | Unsigned Fractional |
11 | Use FORM bits | Signed Fractional |
xx | Quantized Double | Quantized Double |
ADC Sampling and Conversion
Automatic Sample and Triggered Conversion Sequence [2]
The actual MCADC module can be configured to operate in different modes. Below is a list of the possible configurations for the actual MCADC:
- Manual Sample and Manual Conversion Sequence
- Manual Sample and Automatic Conversion Sequence
- Manual Sample and Triggered Conversion Sequence
- Automatic Sample and Manual Conversion Sequence
- Automatic Sample and Automatic Conversion Sequence
- Automatic Sample and Triggered Conversion Sequence
In the PLECS MCADC module only the Automatic Sample and Triggered Conversion Sequence mode has been modeled. The figure above summarizes the operation of this mode.
In this mode, the sampling of the channels starts automatically after a conversion is completed. Automatic sampling is enabled by setting the ASAM bit in the ADCON1 register. The conversion is started upon trigger event from one of the external SOC trigger sources. This allows ADC conversion to be synchronized with the internal or external events. The external trigger source is selected by configuring the SSRC bits to
when using External Interrupt Trigger
or
when using Timer Interrupt Trigger
or
when using Motor Control PWM Special Event Trigger
Note In the PLECS MCADC module, clearing the ASAM bit is not allowed. This bit must always be set. Additionally, in the actual hardware the ADC module takes some time to stabilize. There is no such requirement in the implemented MCADC module.
The MCADC can be operated either as a single-channel 12-bit or multi-channel
10-bit module. The time required to complete a conversion () is dependent
on whether the ADC is operated in 12-bit or 10-bit mode. The table below
summarizes the amount of time required to completed one conversion in the two
modes:
Mode | TCONV |
10-bit | 12 · TAD |
12-bit | 14 · TAD |
Multi-channel ADC Sampling Mode
The MCADC works as single channel converter when operated in as a 12-bit ADC
module. In this mode the inputs to ,
, and
are ignored
and only
is converted. When operated as a 10-bit ADC module, the
MCADC can be configured to operate as a multi-channel ADC module. In the
multi-channel operation, the MCADC module can be configured to operate in
simultaneous or sequential sampling modes. In simultaneous sampling mode, the
sampling of all channels is stopped when an SOC trigger is received. The
figure below shows the timing diagram of a 4-channel module operated with
simultaneous sampling in the Automatic Sample and Triggered Conversion Sequence
mode.
4-Channel Simultaneous Sampling [2]
When the multi-channel ADC module is operated in sequential mode, the
sampling for ends when an SOC trigger is received. The sampling of
ends once the conversion of
is completed. The same logic applies to the end of
sampling for
and
. The figure below shows the timing diagram of a
2-channel module operated with sequential sampling in the Automatic Sample and
Triggered Conversion Sequence mode.
2-Channel Sequential Sampling [2]
Note Any SOC trigger received while the MCADC module is converting will be lost. Conversions are started when an SOC trigger is received while the module is sampling all active channels.
ADC Input Selection Mode
The ADCHS0 and ADCHS123 registers are used to configure which analog input
channels are selected as the positive and negative input selections for , and
,
, and
, respectively. The figures below show the two
registers:
ADCHS0 Register Configuration [2]
ADCHS123 Register Configuration [2]
In the MCADC module, each channel can be configured to operate in fixed input selection mode which uses only MUXA, or in alternate input selection mode where both MUXA and MUXB are used. The table below summarizes the effect of the control bits on the analog input selection for each channel.
When operated in fixed input selection mode, chosen by setting the ALTS bit in
the ADCON2 register to zero, only MUXA and the associated control bits are used
to select the positive and negative analog inputs for each channel. When operated as
a 12-bit module, only is sampled.
When operated in alternate input selection mode, chosen by setting the ALTS bit
in the ADCON2 register to 1, both MUXA and MUXB are used to select the
positive and negative analog inputs for each channel. Again, when operated as a
12-bit module, only is sampled. In this mode the ADC completes one sweep
using the MUXA selection and uses the MUXB selection in the next sweep.
In the next sweep MUXA is used again. This switch between MUXA and
MUXB continues while the ADC is operated in this mode. The figure below
shows the operation of a 2-channel module with alternate input selection in
sequential sampling mode. The interrupt has been configured to occur after 4
conversions.
2-Channel Sequential Sampling in Alternate Input Selection mode [2]
The MCADC module provides further flexibility by allowing to be
operated in scan mode. The Channel Scanning mode is enabled by setting the
Channel Scan bit (CSCNA) in the ADCON2 register.
2-Channel Sequential Sampling in Alternate Input Selection mode with Channel Scan
enabled [2]
The desired conversion sequence is selected by configuring the appropriate bits in
the channel selection register (AD1CSSL). The conversions are carried out in
ascending order. If operated in alternate input selection mode with channel scan
enabled, MUXA software control is ignored for and the ADC module converts
the first selected analog input. In the next sweep, the inputs selected by MUXB are
measured. In the following sweep the next selected analog input is sampled for
. Input selections for
,
, and
are unaffected. The figure
above shows an example of a 2-channel sequential sampling module operated in
alternate input selection mode with channel scanning enabled.
and
have been selected for channel scanning and
has been selected
by the MUXB input selector for
. An interrupt is generated after 8
conversions.
ADC Interrupt Logic
CHPS | SIMSAM | SMPI | Conversions per Interrupt | Description |
00 | x | N-1 | N | 1-Channel mode |
01 | 0 | N-1 | N | 2-Channel, Sequential Sampling mode |
1x | 0 | N-1 | N | 4-Channel, Sequential Sampling mode |
01 | 1 | N-1 | 2 · N | 2-Channel, Simultaneous Sampling mode |
1x | 1 | N-1 | 4 · N | 4-Channel, Simultaneous Sampling mode |
The PLECS MCADC module reflects the properties of an actual MCADC module without DMA. The ADC module writes the results of the conversions into the analog-to-digital result buffer as conversions are completed. The SMPI bits in the ADCON2 register determine the number of conversions for the MCADC module before an interrupt is generated. The results are written into the ADC buffer after each conversion is completed. The MCADC module supports 16 result buffers. Therefore, the maximum number of conversions per interrupt must not exceed 16.
The number of conversions per ADC interrupt depends on the following parameters, which can vary from one to 16 conversions per interrupt:
- Number channels selected
- Sequential or Simultaneous Sampling
- Samples Convert Sequences Per Interrupt bits (SMPI) settings
The table above summarizes the effect each of these factors has on the number of conversions per interrupt.
ADC Buffer Fill Mode
When the Buffer Fill Mode bit (BUFM) in the ADCON2 register is set, the 16-word results buffer is split into two 8-word groups: a lower group (ADC1BUF0 through ADC1BUF7) and an upper group (ADC1BUF8 through ADC1BUFF). The 8-word buffers alternately receive the conversion results after each ADC interrupt event. When the BUFM bit is set, each buffer size equals eight. Therefore, the maximum number of conversions per interrupt must not exceed 8. When the BUFM bit is cleared, the complete 16-word buffer is used for all conversion sequences.
Summary of PLECS Implementation
The PLECS MCADC module models the major functionality of the actual MCADC module. Below is a summary of differences of the PLECS MCADC module compared to the actual MCADC module:
- The PLECS MCADC module models the Microchip MCADC module without DMA.
- The GP timer triggers (Timer 3 and Timer 5) and the Motor Control PWM 1 and 2 triggers have been lumped together into single Timer and PWM trigger, respectively.
- ADCS values over 63 in the ADCON3 register will be flagged as an error in the PLECS MCADC module.
- Only Automatic Sample and Triggered Conversion Sequence mode is supported by the PLECS MCADC module. Clearing the ASAM bit in the ADCON1 register will be flagged as an error.
- The PLECS MCADC module does not require any time for stabilization during startup.
- Any SOC trigger received while the MCADC module is converting will be lost. Conversions are started when an SOC trigger is received while the module is sampling all active channels.
- The output results are provided according to the numerical format specified by the FORM bits in the ADCON1 register or as quantized double values.
Reference
- 1 - Motor Control PWM Reference Guide, Literature Number DS70187E, February 2007 - Revised September 2012
- 2 - Motor Control ADC Reference Guide, Literature Number DS70183D, December 2006 - Revised April 2012