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TI C2000 ADC Type 3 GUI

Purpose

High fidelity model of TI's C2000 ADC module with Graphical User Interface configuration.

Library

Processor in the Loop / Peripherals / TI C2000 / ADC

Description

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This block models the TI Type 3 ADC module. With the Graphical User Interface, the block can simply be configured using combo boxes in the component mask. Under the hood, the resulting register configuration is forwarded to the register based implementation of the TI Type 3 ADC module. The resulting register configuration further is accessible via the probe signals.

For a detailed description of the supported features and the usage of the block please refer to the detailed documentation Analog Digital Converter (ADC) Type 3.

Parameters

ADC General

System Clock [Hz]
The system clock of the processor defined in Hz.
ADCCTL2.CLKDIV4EN
Register cell defining a clock prescaler.
ADCCTL2.CLKDIV2EN
Register cell defining a clock prescaler.
ADCCTL1.ADCREFSEL
Register cell choosing the reference voltage.
External Reference [LO,HI]
Specification of external reference voltage in mask.
ADCCTL1.INTPULSEPOS
Defines position of EOC and interrupt flags.
ADCCTL1.ADCNONOVERLAP
Allows/Inhibits overlap of conversion and sampling.
Output Mode
Defines representation of conversion results.

ADC INTSELxNy

INTSELxNy.INTxE
Enables interrupt generation for INTx.
INTSELxNy.INTxSEL
Defines trigger (EOC flag) for INTx.

ADCSOCx/y

ADCSOCxCTL.TRIGSEL
Defines trigger source for SOCx.
ADCINTSOCSEL1.SOCx
Defines SOCx trigger to be an interrupt. Overwrites TRIGSEL selection if not chosen to NO ADCINT.
ADCSOCxCTL.CHSEL
Selects input channel converted by SOCx.
ADCSOCxCTL.ACQPS
Defines length of sampling window for SOCx.
ADCSAMPLEMODE.SIMULENx
Defines sample mode for SOCx/SOCx+1 pair.

Probe Signals

ADCCTLx
ADC Control registers resulting from mask settings.
ADCSAMPLEMODE
Sample mode control register resulting from mask settings.
ADCSOCxCTL
ADC SOC control registers resulting from mask settings.
INTSELxNy
ADC interrupt module control registers resulting from mask settings.
ADCINTSOCSELx
ADC SOC interrupt trigger control registers resulting from mask settings.