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TI C2000 ePWM Type 4 REG

Purpose

High fidelity model of TI's C2000 ePWM module with register based configuration.

Library

Processor in the Loop / Peripherals / TI C2000 / ePWM

Description

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This block efficiently models the behavior of a single TI Type 4 ePWM module with full timing resolution for a variable PWM period. Beneath the typical PWM generation it also supports the features provided by the Event Trigger and the Deadband submodule. The block is configured using register values which closely emulates the hardware implementation. The registers can be entered in decimal (15), binary (0b1111) or hexadecimal (0xF) representation.

For a detailed description of the supported features and the usage of the block please refer to the detailed documentation Enhance Pulse Width Modulator (ePWM) Type 4.

Parameters

System Clock [Hz]
The system clock of the processor defined in Hz.
EPWM Prescaler
Prescaler to divide down the system clock to generate the EPWM clock.
TBCTL
Time-Base control register.
CMPCTL
Compare control register.
CMPCTL
Compare control register 2.
AQSFRC
Action-Qualifier software force register.
ETSEL
Event-Trigger selection register.
ETPS
Event-Trigger prescale register.
ETCNTINIT
Event-Trigger counter initialization register.
ETSOCPS
Event-Trigger SOC prescale register.
DBCTL
Dead-Band control register.

Probe Signals

CMPx
Compare register.
AQCTLx
Action qualifier configuration.
AQCTLx2
Action qualifier configuration.
AQCSFRC
Action qualifier software forcing configuration.
EPWMx
EPWM outputs.
EPWMSOCx
EPWM SOC pulse outputs.
TBPRD
Period of PWM counter.
TBCTL
Time-Base control register.
CMPCTL
Compare-Control register.
CMPCTL2
Compare-Control register 2.
AQSFRC
Action-Qualifier software force register.
ETSEL
Event-Trigger selection register.
ETPS
Event-Trigger prescale register.
ETCNTINIT
Event-Trigger counter initialization register.
ETSOCPS
Event-Trigger SOC prescaler register.
DBCTL
Dead-Band control register.
DBRED
Dead-Band generator rising-edge delay register.
DBRED
Dead-Band generator falling-edge delay register.