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TI C2000 ADC Type 2 REG

Purpose

High fidelity model of TI's C2000 ADC module with register based configuration.

Library

Processor in the Loop / Peripherals / TI C2000 / ADC

Description

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This block models the TI Type 2 ADC module. The block is configured using register values which closely emulates the hardware implementation. The registers can be entered in decimal (15), binary (0b1111) or hexadecimal (0xF) representation.

For a detailed description of the supported features and the usage of the block please refer to the detailed documentation Analog Digital Converter (ADC) Type 2.

Parameters

HSPCLK [Hz]
The system clock of the processor defined in Hz.
Vref [VREFLO, VREFH]
Specification of reference voltage in mask.
ADCTRLx
ADC Control register x.
ADCCHSELSEQx
ADC Channel select register x.
Output Mode
Defines representation of conversion results.
Sequencer x Reset
Determines reset of Sequencer x state-pointer either internally after an EOS event or externally through the RST_SEQx input.

Probe Signals

Pending SEQx Trigger
Pending trigger for SEQx.
SOC Flag
Start of conversion flag for ADC.
EOS Flag for SEQx
Generates an end-of-sequence signal for SEQx.
ADCCTLx
ADC Control registers resulting from mask settings.
ADCMAXCONV
Maximum ADC conversions resulting from MAX_CONV1 and MAX_CONV2 inputs.
ADCCHSELSEQx
ADC Channel select resulting from mask settings.