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Single-Phase Battery Charger

This demonstration shows a grid-connected battery charger with cascaded AC/DC and DC/DC converters. The AC/DC converter is regulated by a digital PI controller to achieve power factor correction (PFC) and maintain the DC bus voltage at 300 VDC. The DC/DC converter is designed to provide a maximum 120 VDC output at a power rating of 1.4 kW.

Note that this model contains model initializations in the InitFcn model callback, which can be accessed from the File menu, in the Callbacks tab of the Model Properties window.

AC/DC Converter

The AC/DC converter is connected on the AC side via a single stage low pass filter. The topology is an interleaved PFC boost converter, as described in Microchip's application note (AN1278) [1].

Digital control loops for voltage and current regulation are implemented to achieve power factor correction and regulate the DC side voltage to a desired level. The DC side voltage is sampled and compared to the target bus voltage setpoint. The digital voltage compensator with anti-windup sets a DC current setpoint. This DC setpoint is converted into an AC current setpoint to achieve PFC.

The current compensator determines a voltage setpoint, which is converted to a duty cycle. The duty cycle is then used by two symmetrical interleaved PWM blocks.

DC/DC Converter

The DC/DC converter implementation is based on a phase-shifted resonant converter, as described in the demo model Phase Shift DC-DC Converter with Integrated Magnetics [2].

Simulation Results

Run the simulation with the model as provided to view the grid side, bus capacitor, and load voltage waveforms. The AC/DC converter is regulated to maintain the bus voltage at 300 VDC.

Initially the output voltage is regulated to 96 VDC, and at t=0.2 s, the output reference voltage is stepped to 120 VDC. This voltage step change causes the bus capacitor to sag as it is discharged to provide increased load current. The voltage is regulated back to the 300 VDC setpoint by the AC/DC converter. The bus capacitor voltage can be seen in the "DC Bus" plot, shown above.

At t=0.35 s, the output reference voltage is maintained at 120 VDC and the load is doubled. The bus capacitor is again discharged by the increase in load current. The output current, voltage, and power waveforms can be seen in the "Output" plot, shown above.

The AC/DC and DC/DC converter result in PFC, as can be seen in the "AC Input" plot, shown below.

References

[1] - V. Skanda and A. Nahar, "Interleaved Power Factor Correction (IPFC) Using the dsPICĀ® DSC" (DS01278A), Microchip Technology, 2009.

[2] - U. Badstuebner, J. Biela, B. Faessler, D. Hoesli and J.W. Kolar, "An Optimized 5 kW, 147 W/in3 Telecom Phase-Shift DC-DC Converter with Magnetically Integrated Current Doubler," Applied Power Electronics Conference and Exposition (APEC), 2009, Twenty-Seventh Annual IEEE, pp. 21-27, 15-19 Feb. 2009.