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STM32 F4 Timer Output GUI

Purpose

High fidelity model of the STM32 F4 module with focus on output behavior and Graphical User Interface configuration.

Library

Processor in the Loop / Peripherals / STM32 F4 / Timer

Description

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This block efficiently models the behavior of a STM32 F4 timer module with full timing resolution for a variable PWM period. This component is focussed on PWM generation and therefore on the compare/output features of the timer. With the Graphical User Interface, the block can simply be configured using combo boxes in the component mask. Under the hood, the resulting register configuration is forwarded to the register based implementation of the STM32 F4 timer module. The resulting register configuration further is accessible via the probe signals.

For a detailed description of the supported features and the usage of the block please refer to the detailed documentation System Timer for PWM generation (Output Mode).

Parameters

TIM General

Timer Type
Specifies used timer subtype.
CK_PSC [Hz]
Counter clock frequency defined in Hz.
TIM_PSC
A prescaler for the counter time base calculation.
TIM_CR1.CKD
Determines tdts   used for dead-time calculation.
TIM_CR1.CMS
Defines counter mode.
TIM_CR1.DIR
Defines counter direction in Edge-aligned mode.
TIM_BDTR.DTG
Configures dead-time for advanced timer subtype.

TIM INT Enable

Enables Interrupt flag generation on CCxIF and UIF terminals.

TIM_DIER.CCxIE
Enables pulse on CCxIF terminal.
TIM_DIER.UIE
Enables pulse on UIF terminal.

GPIO Mode

Configuration of output level if output enable circuit is inactive.

GPIOM.OCx
Inactive level for channel x.
GPIOM.OCxN
Inactive level for complementary channel x.

Probe Signals

CCRx
Compare register.
OCxM
Output compare mode.
CCER
Timer Compare enable register.
OCx
Output channels.
OCxN
Complementary output channels.
CCxIF
Compare interrupt flags.
UIF
Update event interrupt flags.
TIM_ARR
Timer auto-reload register.
TIM_CR1
Timer control register 1.
TIM_PSC
Timer prescaler register.
TIM_DIER
Timer interrupt enable register.
TIM_BDTR
Timer dead-time register.