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STM32 F4 Timer Output REG

Purpose

High fidelity model of the STM32 F4 module with focus on output behavior and register based configuration.

Library

Processor in the Loop / Peripherals / STM32 F4 / Timer

Description

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This block efficiently models the behavior of a STM32 F4 timer module with full timing resolution for a variable PWM period. This component is focussed on PWM generation and therefore on the compare/output features of the timer. The block is configured using register values which closely emulates the hardware implementation. The registers can be entered in decimal (15), binary (0b1111) or hexadecimal (0xF) representation.

For a detailed description of the supported features and the usage of the block please refer to the detailed documentation System Timer for PWM generation (Output Mode).

Parameters

Timer Type
Specifies used timer subtype.
CK_PSC [Hz]
Counter clock frequency defined in Hz.
TIM_PSC
A prescaler for the counter time base calculation.
TIM_CR1
Timer control register 1.
TIM_BDTR
Timer dead-time register.
TIM_DIER
Timer interrupt enable register.
GPIO Mode
GPIO Mode configuration register.

Probe Signals

CCRx
Compare register.
OCxM
Output compare mode.
CCER
Timer Compare enable register.
OCx
Output channels.
OCxN
Complementary output channels.
CCxIF
Compare interrupt flags.
UIF
Update event interrupt flags.
TIM_ARR
Timer auto-reload register.
TIM_CR1
Timer control register 1.
TIM_PSC
Timer prescaler register.
TIM_DIER
Timer interrupt enable register.
TIM_BDTR
Timer dead-time register.