SR Flip-flop
Purpose
Implement set-reset flip-flop
Library
Control / Logical
Description
The SR Flip-flop behaves like a pair of cross-coupled NOR logic gates. The output values correspond to the following truth table:
S | R | Q | /Q |
0 | 0 | No change | No change |
0 | 1 | 0 | 1 |
1 | 0 | 1 | 0 |
1 | 1 | Restricted (0) | Restricted (0) |
The combination S = R = 1 is restricted because both outputs will be set to 0, violating the condition Q = not(/Q). If both inputs change from 1 to 0 in the same simulation step, Q will be set to 0 and /Q to 1.
Parameters
- Initial state
- The state of the flip-flop at simulation start.
Probe Signals
- S
- The input signal S.
- R
- The input signal R.
- Q
- The output signals Q.
- /Q
- The output signals /Q.