PLECS Workshop

PIL / HIL Simulation and ​Advanced Modeling of Power Electronic Systems

08:30

Registration

09:00

C-Code Integration

  • Solver operation

  • Sample time settings

  • DLL Block

Exercise: Efficient PWM generation using the PLECS C-Script block

10:15

Break

10:30

C-Code Integration (Continuation)

  • Solver operation

  • Sample time settings

  • DLL Block

Exercise: Efficient PWM generation using the PLECS C-Script block

12:00

Lunch

13:00

Analysis Tools (Multitone Analysis)

  • Steady state analysis

  • AC sweep and impulse response analysis

14:00

Principle of a Processor-in-the-Loop (PIL) Simulation

  • Integration of PIL

  • Integration of the PIL framework into an embedded project

  • Setting up PLECS for PIL

15:00

Pause

15:15

Hardware-in-the-Loop (HIL) Simulation using the PLECS RT Box

  • Basic hardware structure

  • Difference between models in HIL and offline-simulation

  • Technologies for large scale models in HIL

  • Demo of different power electronic systems

16:00

What's New in PLECS / Q&A

16:30

End of Workshop

 

This workshop addresses to anyone who already has experience with the simulation software PLECS.

 

City: 
Warsaw
Country: 
Poland
Date: 
Mercredi, février 1st, 2017 - 8:30 am
Speaker: 

To be announced

Registration: 

Roman Troesch
troesch@plexim.com, +41 (0)44 533 51 18

Venue: 

Warsaw University of Technology
Main Building (Gmach Główny)
Room 443
Pl. Politechniki 1
00-661 Warszawa
Poland